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CY7C1021CV26-15ZSXET PDF预览

CY7C1021CV26-15ZSXET

更新时间: 2024-11-11 09:43:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
15页 518K
描述
1-Mbit (64 K × 16) Static RAM

CY7C1021CV26-15ZSXET 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:TSOP2包装说明:TSOP2, TSOP44,.46,32
针数:44Reach Compliance Code:compliant
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
Factory Lead Time:1 week风险等级:5.35
Is Samacsys:N最长访问时间:15 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-G44
JESD-609代码:e4长度:18.415 mm
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:16湿度敏感等级:3
功能数量:1端子数量:44
字数:65536 words字数代码:64000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-40 °C组织:64KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSOP44,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:2.6 V认证状态:Not Qualified
筛选级别:AEC-Q100座面最大高度:1.194 mm
最大待机电流:0.01 A最小待机电流:2.5 V
子类别:SRAMs最大压摆率:0.08 mA
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.5 V
标称供电电压 (Vsup):2.6 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:10.16 mm
Base Number Matches:1

CY7C1021CV26-15ZSXET 数据手册

 浏览型号CY7C1021CV26-15ZSXET的Datasheet PDF文件第2页浏览型号CY7C1021CV26-15ZSXET的Datasheet PDF文件第3页浏览型号CY7C1021CV26-15ZSXET的Datasheet PDF文件第4页浏览型号CY7C1021CV26-15ZSXET的Datasheet PDF文件第5页浏览型号CY7C1021CV26-15ZSXET的Datasheet PDF文件第6页浏览型号CY7C1021CV26-15ZSXET的Datasheet PDF文件第7页 
CY7C1021CV26  
1-Mbit (64 K × 16) Static RAM  
1-Mbit (64  
K × 16) Static RAM  
an automatic power-down feature that significantly reduces  
power consumption when deselected.  
Features  
Temperature Range  
Automotive: –40 °C to 125 °C  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is  
written into the location specified on the address pins (A0  
through A15). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O9 through I/O16) is written into the location  
specified on the address pins (A0 through A15).  
High speed  
tAA = 15 ns  
Optimized voltage range: 2.5 V to 2.7 V  
Low active power: 220 mW (Max)  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O9 to I/O16. See  
the truth table at the end of this data sheet for a complete  
description of Read and Write modes.  
Automatic power-down when deselected  
Independent control of upper and lower bits  
CMOS for optimum speed/power  
Available in Pb-free and non Pb-free 44-pin TSOP II , 44-pin  
(400-Mil) Molded SOJ and Pb-free 48-ball FPBGA packages  
The input/output pins (I/O1 through I/O16) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a Write operation  
(CE LOW, and WE LOW).  
Functional Description  
The CY7C1021CV26 is a high-performance CMOS static  
RAM organized as 65,536 words by 16 bits. This device has  
Logic Block Diagram  
DATA IN DRIVERS  
A7  
A6  
A5  
A4  
A3  
A2  
64K x 16  
I/O1–I/O8  
RAM Array  
I/O9–I/O16  
A1  
A0  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Cypress Semiconductor Corporation  
Document Number: 38-05589 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised December 1, 2010  
[+] Feedback  

CY7C1021CV26-15ZSXET 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1021CV26-15ZSXE CYPRESS

完全替代

1-Mbit (64K x 16) Static RAM
CY7C1021CV26-15ZE CYPRESS

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1-Mbit (64K x 16) Static RAM

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