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CY7C1019D-10ZSXIT PDF预览

CY7C1019D-10ZSXIT

更新时间: 2024-11-14 20:04:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
16页 780K
描述
Standard SRAM, 128KX8, 10ns, CMOS, PDSO32,

CY7C1019D-10ZSXIT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:TSOP, TSOP32,.46
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.78
最长访问时间:10 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G32JESD-609代码:e3
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:8湿度敏感等级:3
端子数量:32字数:131072 words
字数代码:128000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:128KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP
封装等效代码:TSOP32,.46封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
电源:5 V认证状态:Not Qualified
最大待机电流:0.003 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.08 mA
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

CY7C1019D-10ZSXIT 数据手册

 浏览型号CY7C1019D-10ZSXIT的Datasheet PDF文件第2页浏览型号CY7C1019D-10ZSXIT的Datasheet PDF文件第3页浏览型号CY7C1019D-10ZSXIT的Datasheet PDF文件第4页浏览型号CY7C1019D-10ZSXIT的Datasheet PDF文件第5页浏览型号CY7C1019D-10ZSXIT的Datasheet PDF文件第6页浏览型号CY7C1019D-10ZSXIT的Datasheet PDF文件第7页 
CY7C1019D  
1-Mbit (128 K × 8) Static RAM  
1-Mbit (128  
K × 8) Static RAM  
Features  
Functional Description  
[1]  
Pin- and function-compatible with CY7C1019B  
The CY7C1019D  
is a high-performance CMOS static RAM  
organized as 131,072 words by 8 bits. Easy memory expansion  
is provided by an active LOW Chip Enable (CE), an active LOW  
Output Enable (OE), and tri-state drivers. This device has an  
automatic power-down feature that significantly reduces power  
consumption when deselected. The eight input and output pins  
(IO0 through IO7) are placed in a high-impedance state when:  
High speed  
tAA = 10 ns  
Low active power  
ICC = 80 mA @ 10 ns  
Low CMOS standby power  
ISB2 = 3 mA  
Deselected (CE HIGH)  
Outputs are disabled (OE HIGH)  
2.0 V Data retention  
When the write operation is active (CE LOW, and WE LOW).  
Automatic power-down when deselected  
CMOS for optimum speed/power  
Center power/ground pinout  
Write to the device by taking Chip Enable (CE) and Write Enable  
(WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is  
then written into the location specified on the address pins (A0  
through A16).  
Easy memory expansion with CE and OE options  
Functionally equivalent to CY7C1019B  
Read from the device by taking Chip Enable (CE) and Output  
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under  
these conditions, the contents of the memory location specified  
by the address pins appears on the IO pins.  
Available in Pb-free 32-pin 400-Mil wide Molded SOJ and  
32-pin TSOP II packages  
The CY7C1019D device is suitable for interfacing with  
processors that have TTL I/P levels. It is not suitable for  
processors that require CMOS I/P levels. Please see Electrical  
Characteristics on page 4 for more details and suggested  
alternatives.  
For a complete list of related documentation, click here.  
Logic Block Diagram  
IO  
0
INPUT BUFFER  
IO  
1
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
IO  
2
128K x 8  
ARRAY  
IO  
3
IO  
4
IO  
5
IO  
6
CE  
IO  
POWER  
DOWN  
7
COLUMN DECODER  
WE  
OE  
Note  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document Number: 38-05464 Rev. *J  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised November 26, 2014  
 
 

CY7C1019D-10ZSXIT 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1019D-10ZSXI CYPRESS

完全替代

1-Mbit (128K x 8) Static RAM

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