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CY7C1019DL-10ZXI PDF预览

CY7C1019DL-10ZXI

更新时间： 2024-11-15 10:25:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管
页数 文件大小 规格书
9页 196K
描述
Standard SRAM, 128KX8, 10ns, CMOS, PDSO32

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CY7C1019DL-10ZXI 数据手册

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CY7C1019D  
PRELIMINARY  
1-Mbit (128K x 8) Static RAM  
Features  
Functional Description[1]  
• Pin- and function-compatible with CY7C1019B  
• High speed  
The CY7C1019D is a high-performance CMOS static RAM  
organized as 131,072 words by 8 bits. Easy memory  
expansion is provided by an active LOW Chip Enable (CE), an  
active LOW Output Enable (OE), and tri-state drivers. This  
device has an automatic power-down feature that significantly  
reduces power consumption when deselected.  
— tAA = 10 ns  
• CMOS for optimum speed/power  
• Low active power  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. Data on the eight  
I/O pins (I/O0 through I/O7) is then written into the location  
specified on the address pins (A0 through A16).  
— ICC = 60 mA @ 10 ns  
• Low CMOS standby power  
— ISB2 = 1.2 mA (‘L’ Version only)  
• Data Retention at 2.0V  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the I/O pins.  
• Center power/ground pinout  
• Automatic power-down when deselected  
• Easy memory expansion with CE and OE options  
• Functionally equivalent to CY7C1019B  
• Available in Pb-Free Packages  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
The CY7C1019D is available in standard 32-pin TSOP Type  
II and 400-mil-wide SOJ Pb-Free packages.  
Logic Block Diagram  
Pin Configurations  
/TSOPII  
SOJ  
Top View  
A
A
1
A
A
32  
1
0
16  
31  
30  
2
3
4
5
6
15  
A
2
A
14  
A
13  
A
29  
28  
3
I/O  
0
CE  
I/O  
OE  
I/O  
I/O  
6
INPUT BUFFER  
27  
26  
0
7
I/O  
I/O  
1
2
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
I/O  
7
1
25  
24  
23  
22  
21  
V
V
8
9
10  
11  
12  
13  
V
V
CC  
I/O  
5
I/O  
CC  
SS  
SS  
I/O  
3
I/O  
4
I/O  
5
512 x 256 x 8  
ARRAY  
I/O  
I/O  
2
3
4
A
A
A
WE  
12  
11  
A
4
20  
19  
A
5
10  
I/O  
14  
15  
16  
6
7
POWER  
DOWN  
COLUMN  
DECODER  
CE  
WE  
A
6
A
9
A
8
18  
17  
I/O  
A
7
OE  
Note:  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05464 Rev. *C  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised January 11, 2005  
1234567...9

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