Datasheet > CY7C1019DV33

CY7C1019DV33

更新时间： 2024-11-14 03:14:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
11页	387K
描述
1-Mbit (128K x 8) Static RAM

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CY7C1019DV33 数据手册

CY7C1019DV33

1-Mbit (128K x 8) Static RAM

Features

Functional Description^[1]

• Pin- and function-compatible with CY7C1019CV33

• High speed

The CY7C1019DV33 is a high-performance CMOS static

RAM organized as 131,072 words by 8 bits. Easy memory

expansion is provided by an active LOW Chip Enable (CE), an

active LOW Output Enable (OE), and three-state drivers. This

device has an automatic power-down feature that significantly

reduces power consumption when deselected.

— t_AA= 10 ns

• Low Active Power

— I_CC= 60 mA @ 10 ns

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O

pins (I/O₀through I/O₇) is then written into the location

specified on the address pins (A₀through A₁₆).

• Low CMOS Standby Power

— I_SB2= 3 mA

• 2.0V Data retention

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Center power/ground pinout

• Easy memory expansion with CE and OE options

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing Write

Enable (WE) HIGH. Under these conditions, the contents of

the memory location specified by the address pins will appear

on the I/O pins.

• Available in Pb-free 32-pin 400-Mil wide Molded SOJ,

32-pin TSOP II and 48-ball VFBGA packages

The eight input/output pins (I/O₀through I/O₇) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), or during a write

operation (CE LOW, and WE LOW).

The CY7C1019DV33 is available in Pb-free 32-pin 400-Mil

wide Molded SOJ, 32-pin TSOP II and 48-ball VFBGA

packages.

Logic Block Diagram

I/O

INPUTBUFFER

128K × 8

ARRAY

POWER

DOWN

COLUMN

DECODER

I/O

Note

1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com

Cypress Semiconductor Corporation

Document #: 38-05481 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 8, 2006

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CY7C1019DV33_10	CYPRESS	获取价格	1-Mbit (128K x 8) Static RAM
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CY7C1019DV33-10BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C1019DV-3310VXI	CYPRESS	获取价格	1-Mbit (128 K Ã 8) Static RAM
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CY7C1019DV33-10VXI	INFINEON	获取价格	Asynchronous SRAM
CY7C1019DV33-10VXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C1019DV33-10ZSXI	CYPRESS	获取价格	1-Mbit (128K x 8) Static RAM
CY7C1019DV33-10ZSXIT	CYPRESS	获取价格	暂无描述