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CY7C1019V33 PDF预览

CY7C1019V33

更新时间： 2024-09-15 21:55:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
7页 155K
描述
128K x 8 Static RAM

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中文翻译

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CY7C1019V33 数据手册

 浏览型号CY7C1019V33的Datasheet PDF文件第2页浏览型号CY7C1019V33的Datasheet PDF文件第3页浏览型号CY7C1019V33的Datasheet PDF文件第4页浏览型号CY7C1019V33的Datasheet PDF文件第5页浏览型号CY7C1019V33的Datasheet PDF文件第6页浏览型号CY7C1019V33的Datasheet PDF文件第7页 
3
CY7C1018V33  
CY7C1019V33  
128K x 8 Static RAM  
pins (I/O through I/O ) is then written into the location speci-  
Features  
0
7
fied on the address pins (A through A ).  
0
16  
• High speed  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the I/O pins.  
— t = 10 ns  
AA  
• CMOS for optimum speed/power  
• Center power/ground pinout  
• Automatic power-down when deselected  
• Easy memory expansion with CE and OE options  
The eight input/output pins (I/O through I/O ) are placed in a  
0
7
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
Functional Description  
The CY7C1018V33/CY7C1019V33 is a high-performance  
CMOS static RAM organized as 131,072 words by 8 bits. Easy  
memory expansion is provided by an active LOW Chip Enable  
(CE), an active LOW Output Enable (OE), and three-state driv-  
ers. This device has an automatic power-down feature that  
significantly reduces power consumption when deselected.  
The CY7C1018V33 is available in a standard 300-mil-wide  
SOJ and CY7C1019V33 is available in  
400-mil-wide package. The CY7C1018V33  
a
standard  
and  
CY7C1019V33 are functionally equivalent in all other re-  
spects.  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O  
Logic Block Diagram  
Pin Configurations  
SOJ  
Top View  
A
A
A
A
32  
31  
30  
1
2
3
4
5
6
0
1
16  
15  
A
A
A
2
14  
13  
I/O  
0
A
29  
28  
3
INPUT BUFFER  
CE  
OE  
I/O  
I/O  
I/O  
1
I/O  
2
27  
26  
I/O  
0
1
A
0
7
A
1
I/O  
V
7
8
9
6
A
2
25  
24  
23  
22  
21  
V
CC  
SS  
A
3
4
V
V
SS  
A
CC  
I/O  
3
I/O  
4
I/O  
5
512 x 256 x 8  
ARRAY  
A
6
I/O  
I/O  
I/O  
5
10  
11  
12  
13  
2
3
5
4
A
I/O  
A
A
7
8
WE  
12  
A
A
A
4
11  
20  
19  
A
5
A
6
A
A
A
10  
14  
15  
16  
I/O  
6
18  
17  
POWER  
DOWN  
9
8
COLUMN  
DECODER  
CE  
A
7
I/O  
7
WE  
1019V33–2  
1019V33–1  
OE  
Selection Guide  
7C1018V33-12  
7C1019V33-12  
7C1018V33-15  
7C1019V33-15  
7C1019V33-10  
Maximum Access Time (ns)  
10  
175  
5
12  
160  
5
15  
145  
5
Maximum Operating Current (mA)  
Maximum Standby Current (mA)  
L
−
0.5  
0.5  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
October 18, 1999  
1234567

中文翻译

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CY7C1019V33-10VC CYPRESS

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 		128K x 8 Static RAM
CY7C1019V33-10VCT CYPRESS

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 		Standard SRAM, 128KX8, 10ns, CMOS, PDSO32, 0.400 INCH, SOJ-32
CY7C1019V33-12VC CYPRESS

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 		128K x 8 Static RAM
CY7C1019V33-12VCT CYPRESS

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CY7C1019V33-15VC CYPRESS

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 		128K x 8 Static RAM
CY7C1019V33-15VCT CYPRESS

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 		Standard SRAM, 128KX8, 15ns, CMOS, PDSO32, 0.400 INCH, SOJ-32
CY7C1019V33L-10VC ETC

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 		x8 SRAM
CY7C1019V33L-12VC CYPRESS

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 		128K x 8 Static RAM
CY7C1019V33L-15VC CYPRESS

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 		128K x 8 Static RAM
CY7C1019V33L-15VCT CYPRESS

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 		Standard SRAM, 128KX8, 15ns, CMOS, PDSO32, 0.400 INCH, SOJ-32

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