Datasheet > CY7C1019DV33-10VXI

CY7C1019DV33-10VXI

更新时间： 2024-11-15 14:51:15

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器光电二极管内存集成电路
页数	文件大小	规格书
20页	553K
描述
Asynchronous SRAM

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中文翻译

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数据手册

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CY7C1019DV33-10VXI 数据手册

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CY7C1018DV33

CY7C1019DV33

1-Mbit (128 K × 8) Static RAM

1-Mbit (128

K × 8) Static RAM

Features

Functional Description

■ Pin- and function-compatible with CY7C1018CV33 and

CY7C1019CV33

The CY7C1018DV33/CY7C1019DV33 is a high-performance

CMOS static RAM organized as 131,072 words by 8 bits. Easy

memory expansion is provided by an active LOW Chip Enable

(CE), an active LOW Output Enable (OE), and three-state

drivers. This device has an automatic power-down feature that

significantly reduces power consumption when deselected.

■ High speed

❐ t_AA= 10 ns

■ Low Active Power

Writing to the device is accomplished by taking Chip Enable (CE)

and Write Enable (WE) inputs LOW. Data on the eight I/O pins

(I/O₀through I/O₇) is then written into the location specified on

the address pins (A₀through A₁₆).

❐ I_CC= 60 mA @ 10 ns

■ Low CMOS Standby Power

❐ I_SB2= 3 mA

■ 2.0 V Data retention

Reading from the device is accomplished by taking Chip Enable

(CE) and Output Enable (OE) LOW while forcing Write Enable

(WE) HIGH. Under these conditions, the contents of the memory

location specified by the address pins will appear on the I/O pins.

■ Automatic power-down when deselected

■ CMOS for optimum speed/power

■ Center power/ground pinout

The eight input/output pins (I/O₀through I/O₇) are placed in a

high-impedance state when the device is deselected (CE HIGH),

the outputs are disabled (OE HIGH), or during a write operation

(CE LOW, and WE LOW).

■ Easy memory expansion with CE and OE options

■ Available in Pb-free 32-pin 400-Mil wide Molded SOJ, 32-pin

The CY7C1018DV33/CY7C1019DV33 are available in Pb-free

32-pin 400-Mil wide Molded SOJ, 32-pin TSOP II and 48-ball

VFBGA packages.

TSOP II and 48-ball VFBGA packages

For a complete list of related documentation, click here.

Logic Block Diagram

I/O

INPUTBUFFER

128K × 8

ARRAY

POWER

DOWN

COLUMN

DECODER

I/O

Cypress Semiconductor Corporation

Document Number: 38-05481 Rev. *J

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 26, 2015

12 3 4 5 6 7...20

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与CY7C1019DV33-10VXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1019DV33-10VXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C1019DV33-10ZSXI	CYPRESS	获取价格	1-Mbit (128K x 8) Static RAM
CY7C1019DV33-10ZSXIT	CYPRESS	获取价格	暂无描述
CY7C1019L-10VC	CYPRESS	获取价格	128K x 8 Static RAM
CY7C1019L-12VC	CYPRESS	获取价格	128K x 8 Static RAM
CY7C1019L-15VC	CYPRESS	获取价格	128K x 8 Static RAM
CY7C1019-V	ATMEL	获取价格	Supports the ATmega2560, ATmega1280 and ATmega640
CY7C1019V33	CYPRESS	获取价格	128K x 8 Static RAM
CY7C1019V33-10VC	CYPRESS	获取价格	128K x 8 Static RAM
CY7C1019V33-10VCT	CYPRESS	获取价格	Standard SRAM, 128KX8, 10ns, CMOS, PDSO32, 0.400 INCH, SOJ-32