CY7C1010DV33
2-Mbit (256 K × 8) Static RAM
2-Mbit (256
K × 8) Static RAM
Features
Functional Description
■ Pin and function compatible with CY7C1010CV33
The CY7C1010DV33 is a high performance CMOS Static RAM
organized as 256 K words by 8 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE), and three-state drivers. Writing to the
device is accomplished by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A17).
■ High speed
❐ tAA = 10 ns
■ Low active power
❐ ICC = 90 mA at 10 ns
■ Low CMOS standby power
❐ ISB2 = 10 mA
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
■ 2.0 V data retention
■ Automatic power down when deselected
■ TTL-compatible inputs and outputs
The eight input and output pins (I/O0 through I/O7) are placed in
a high impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
■ Easy memory expansion with CE and OE features
■ Available in Pb-free 36-pin SOJ and 44-pin TSOP II packages
The CY7C1010DV33 is available in 36-pin SOJ and 44-pin
TSOP II packages with center power and ground (revolutionary)
pinout.
For a complete list of related documentation, click here.
Logic Block Diagram
IO
0
INPUT BUFFER
A
0
IO
1
A
1
A
2
IO
2
A
3
A
4
256K x 8
ARRAY
IO
3
A
A
A
A
A
A
5
6
IO
4
7
8
IO
IO
IO
5
6
7
9
10
CE
POWER
DOWN
COLUMN DECODER
WE
OE
Cypress Semiconductor Corporation
Document Number: 001-00062 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 19, 2014