Datasheet > CY7C1011CV33_10

CY7C1011CV33_10

更新时间： 2024-09-18 09:43:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
16页	552K
描述
2-Mbit (128K x 16) Static RAM

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CY7C1011CV33_10 数据手册

CY7C1011CV33

2-Mbit (128K x 16) Static RAM

Features

Functional Description

■ Temperature ranges

The CY7C1011CV33 is a high performance complementary

metal oxide semiconductor (CMOS) static RAM organized as

131,072 words by 16 bits. This device has an automatic power

down feature that significantly reduces power consumption when

deselected.

❐ Industrial: –40 °C to 85 °C

❐ Automotive-A: –40 °C to 85 °C

❐ Automotive-E: –40 °C to 125 °C

■ Pin and function compatible with CY7C1011BV33

To write to the device, take CE and Write Enable (WE) inputs

LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins

(I/O₀through I/O₇), is written into the location specified on the

address pins (A₀through A₁₆). If Byte High Enable (BHE) is

LOW, then data from I/O pins (I/O₈through I/O₁₅) is written into

the location specified on the address pins (A₀through A₁₆).

■ High speed

❐ t_AA= 10 ns (Industrial and Automotive-A)

❐ t_AA= 12 ns (Automotive-E)

■ Low active power

❐ 360 mW (max) (Industrial and Automotive-A)

To read from the device, take CE and OE LOW while forcing the

Write Enable (WE) HIGH. If BLE is LOW, then data from the

memory location specified by the address pins appear on I/O₀to

I/O₇. If Byte High Enable (BHE) is LOW, then data from memory

appears on I/O₈to I/O₁₅. For more information, see the “Truth

Table” on page 10 for a complete description of Read and Write

modes.

■ 2.0 V data retention

■ Automatic power down when deselected

■ Independent control of upper and lower bits

■ Easy memory expansion with Chip Enable (CE) and Output

Enable (OE) features

The input and output pins (I/O₀through I/O₁₅) are placed in a

high impedance state when the device is deselected (CE HIGH),

the outputs are disabled (OE HIGH), the BHE and BLE are

disabled (BHE, BLE HIGH), or during a write operation (CE LOW

and WE LOW).

■ Available in Pb-free 44-pin thin small outline package

(TSOP) II, 44-pin thin quad flat package (TQFP), and non

Pb-free 48-ball very fine ball grid array (VFBGA) packages

For best practice recommendations, refer to the Cypress 

application note AN1064, SRAM System Guidelines.

Logic Block Diagram

INPUT BUFFER

128K x 16

RAM Array

I/O –I/O

COLUMN DECODER

BHE

BLE

Cypress Semiconductor Corporation

Document Number: 38-05232 Rev. *K

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 18, 2010

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与CY7C1011CV33_10相关器件

型号	品牌	获取价格	描述	数据表
CY7C1011CV33_11	CYPRESS	获取价格	2-Mbit (128 K Ã 16) Static RAM 360 mW (max)
CY7C1011CV33_13	CYPRESS	获取价格	2-Mbit (128 K Ã 16) Static RAM
CY7C1011CV33-10BVC	CYPRESS	获取价格	128K x 16 Static RAM
CY7C1011CV33-10BVI	CYPRESS	获取价格	128K x 16 Static RAM
CY7C1011CV33-10ZC	CYPRESS	获取价格	128K x 16 Static RAM
CY7C1011CV33-10ZCT	CYPRESS	获取价格	Standard SRAM, 128KX16, 10ns, CMOS, PDSO44, TSOP2-44
CY7C1011CV33-10ZI	CYPRESS	获取价格	128K x 16 Static RAM
CY7C1011CV33-10ZSXA	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM
CY7C1011CV33-10ZXC	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM
CY7C1011CV33-10ZXCT	CYPRESS	获取价格	Standard SRAM, 128KX16, 10ns, CMOS, PDSO44, LEAD FREE, TSOP2-44

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