CY7C1011CV33
2-Mbit (128K x 16) Static RAM
Features
Functional Description
• Pin equivalent to CY7C1011BV33
• High speed
The CY7C1011CV33 is a high-performance CMOS Static
RAM organized as 131,072 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
— tAA = 10 ns
• Low active power
— 360 mW (max.)
• Data Retention at 2.0
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Easy memory expansion with CE and OE features
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
• Available in Pb-free and non Pb-free 44-pin TSOP II,
44-pin TQFP and non Pb-free 48-ball VFBGA packages
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1011CV33 is available in a standard 44-pin TSOP
II package with center power and ground pinout, a 44-pin Thin
Plastic Quad Flatpack (TQFP), as well as a 48-ball fine-pitch
ball grid array (VFBGA) package.
Logic Block Diagram
Pin Configuration
TSOP II
Top View
INPUT BUFFER
44
1
A
4
A
5
A
0
43
42
41
40
39
38
A
A
2
3
4
5
6
3
6
A
1
A
A
2
7
A
2
OE
A
1
I/O0–I/O7
128K x 16
ARRAY
A
3
BHE
BLE
I/O
I/O
I/O
A
0
A
4
CE
A
I/O8–I/O15
5
I/O
7
0
15
A
6
37
36
35
34
33
I/O
I/O
8
1
2
14
13
12
A
7
9
A
8
10
11
12
13
I/O
V
SS
I/O
3
CC
V
SS
V
V
CC
COLUMN
DECODER
32
I/O
I/O
I/O
4
5
6
7
11
10
31
30
29
28
I/O
I/O
I/O
14
15
16
I/O
I/O
9
8
WE 17
NC
A
18
19
20
21
22
27
26
25
16
15
A
BHE
8
A
A
A
WE
CE
OE
9
A
11
14
10
A
A
12
24
23
13
BLE
A
NC
Cypress Semiconductor Corporation
Document #: 38-05232 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 6, 2006
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