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CY7C1011CV33 PDF预览

CY7C1011CV33

更新时间： 2024-09-17 22:09:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
11页 334K
描述
128K x 16 Static RAM

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中文翻译

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CY7C1011CV33 数据手册

 浏览型号CY7C1011CV33的Datasheet PDF文件第2页浏览型号CY7C1011CV33的Datasheet PDF文件第3页浏览型号CY7C1011CV33的Datasheet PDF文件第4页浏览型号CY7C1011CV33的Datasheet PDF文件第5页浏览型号CY7C1011CV33的Datasheet PDF文件第6页浏览型号CY7C1011CV33的Datasheet PDF文件第7页 
CY7C1011CV33  
128K x 16 Static RAM  
written into the location specified on the address pins (A0  
through A16). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A16).  
Features  
• Pin equivalent to CY7C1011BV33  
• High speed  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
— tAA = 10 ns  
• Low active power  
— 360 mW (max.)  
• Data Retention at 2.0  
• Automatic power-down when deselected  
• Independent control of upper and lower bits  
• Easy memory expansion with CE and OE features  
The input/output pins (I/O0 through I/O15) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
• Available in 44-pin TSOP II, 44-pin TQFP, and 48-ball  
VFBGA  
Functional Description  
The CY7C1011CV33 is a high-performance CMOS Static  
RAM organized as 131,072 words by 16 bits.  
The CY7C1011CV33 is available in a standard 44-pin TSOP  
II package with center power and ground pinout, a 44-pin Thin  
Plastic Quad Flatpack (TQFP), as well as a 48-ball fine-pitch  
ball grid array (VFBGA) package.  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
Logic Block Diagram  
Pin Configuration  
TSOP II  
Top View  
INPUT BUFFER  
44  
1
A
4
A
5
A
0
43  
42  
41  
40  
39  
38  
A
A
2
3
4
5
6
3
6
A
1
A
A
2
7
A
2
OE  
A
1
I/O – I/O  
256K x 16  
ARRAY  
0
7
A
3
4
BHE  
BLE  
I/O  
I/O  
I/O  
A
0
A
CE  
1024 x 4096  
A
I/O – I/O  
5
6
8
15  
I/O  
7
0
15  
A
37  
36  
35  
34  
33  
I/O  
I/O  
8
1
2
14  
13  
12  
A
7
8
9
A
10  
11  
12  
13  
I/O  
V
SS  
I/O  
3
CC  
V
SS  
V
V
CC  
COLUMN  
DECODER  
32  
I/O  
I/O  
I/O  
4
5
6
7
11  
10  
I/O  
I/O  
I/O  
31  
30  
29  
28  
14  
15  
16  
I/O  
I/O  
9
8
WE 17  
NC  
A
18  
15 19  
20  
27  
26  
25  
16  
A
BHE  
8
A
A
9
WE  
CE  
OE  
A
A
A
A
11  
14  
13  
10  
21  
22  
A
24  
23  
BLE  
NC  
12  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05232 Rev. *B  
Revised October 10, 2002  
1234567...11

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 		Standard SRAM, 128KX16, 10ns, CMOS, PDSO44, TSOP2-44

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