Datasheet > CY7C027_05

CY7C027_05

更新时间： 2024-11-07 04:10:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
20页	492K
描述
32K/64K x 16/18 Dual-Port Static RAM

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中文翻译

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数据手册

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CY7C027_05 数据手册

CY7C027/028

CY7C037/03832K/64K

x 16/18 Dual-Port Static RAM

CY7C027/028

CY7C037/038

32K/64K x 16/18 Dual-Port Static RAM

• Automatic power-down

Features

• Expandable data bus to 32/36 bits or more using

Master/Slave chip select when using more than one

device

• True Dual-Ported memory cells which allow simulta-

neous access of the same memory location

• 32K x 16 organization (CY7C027)

• 64K x 16 organization (CY7C028)

• 32K x 18 organization (CY7C037)

• 64K x 18 organization (CY7C038)

• 0.35-micron CMOS for optimum speed/power

• High-speed access: 12^[1]/15/20 ns

• Low operating power

• On-chip arbitration logic

• Semaphores included to permit software handshaking

between ports

• INT flags for port-to-port communication

• Separate upper-byte and lower-byte control

• Dual Chip Enables

• Pin select for Master or Slave

— Active: I_CC= 180 mA (typical)

— Standby: I_SB3= 0.05 mA (typical)

• Fully asynchronous operation

• Commercial and industrial temperature ranges

• Available in 100-pin TQFP

• Pb-Free packages available

Logic Block Diagram

R/W_L

UB_L

R/W_R

UB_R

CE_0L

CE_0R

CE_1L

CE_1R

CE_L

CE_R

LB_L

LB_R

OE_L

OE_R

8/9

[2]

8/9

[2]

I/O_8/9L–I/O_15/17L

I/O_8/9L–I/O_15/17R

8/9

I/O

Control

[3]

I/O_0L–I/O_7/8L

Control

I/O_0L–I/O_7/8R

15/16

Address

Decode

Address

Decode

True Dual-Ported

[4]

A_0L–A_14/15L

A_0R–A_14/15R

RAM Array

15/16

[4]

A_0L–A_14/15L

A_0R–A_14/15R

CE_L

CE_R

OE_R

Interrupt

Semaphore

Arbitration

OE_L

R/W_L

SEM_L

R/W_R

SEM_R

[5]

BUSY_L

BUSY_R

INT_L

UB_L

LB_L

INT_R

UB_R

LB_R

M/S

Notes:

1. See page 6 for Load Conditions.

2. I/O –I/O for x16 devices; I/O –I/O for x18 devices.

3. I/O –I/O for x16 devices; I/O –I/O for x18 devices.

4. A –A for 32K; A –A for 64K devices.

5. BUSY is an output in master mode and an input in slave mode.

Cypress Semiconductor Corporation

Document #: 38-06042 Rev. *C

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised June 13, 2005

12 3 4 5 6 7...20

中文翻译

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与CY7C027_05相关器件

型号	品牌	获取价格	描述	数据表
CY7C027-12AC	CYPRESS	获取价格	32K/64K x 16/18 Dual-Port Static RAM
CY7C027-15AC	CYPRESS	获取价格	32K/64K x 16/18 Dual-Port Static RAM
CY7C027-15AI	CYPRESS	获取价格	Dual-Port SRAM, 32KX16, 15ns, CMOS, PQFP100, PLASTIC, TQFP-100
CY7C027-15AXI	CYPRESS	获取价格	暂无描述
CY7C027-20AC	CYPRESS	获取价格	32K/64K x 16/18 Dual-Port Static RAM
CY7C027-20ACT	CYPRESS	获取价格	Dual-Port SRAM, 32KX16, 20ns, CMOS, PQFP100, PLASTIC, TQFP-100
CY7C027-20AI	CYPRESS	获取价格	Dual-Port SRAM, 32KX16, 20ns, CMOS, PQFP100, PLASTIC, TQFP-100
CY7C027-20AXC	CYPRESS	获取价格	32K/64K x 16/18 Dual-Port Static RAM
CY7C027-20AXCT	CYPRESS	获取价格	Multi-Port SRAM, 32KX16, 20ns, CMOS, PQFP100, ROHS COMPLIANT, PLASTIC, MS-026, TQFP-100
CY7C027AV-25AXI	CYPRESS	获取价格	3.3V 32K/64K x 16/18 Dual-Port Static RAM