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CY7C027V-25AI PDF预览

CY7C027V-25AI

更新时间: 2024-11-09 12:59:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
22页 336K
描述
Dual-Port SRAM, 32KX16, 25ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100

CY7C027V-25AI 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, MS-026, TQFP-100
针数:100Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
Factory Lead Time:1 week风险等级:5.48
Is Samacsys:N最长访问时间:25 ns
其他特性:AUTOMATIC POWER-DOWNI/O 类型:COMMON
JESD-30 代码:S-PQFP-G100JESD-609代码:e0
长度:14 mm内存密度:524288 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端口数量:2端子数量:100
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:32KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP100,.63SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):235
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.0001 A
最小待机电流:3 V子类别:SRAMs
最大压摆率:0.185 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

CY7C027V-25AI 数据手册

 浏览型号CY7C027V-25AI的Datasheet PDF文件第2页浏览型号CY7C027V-25AI的Datasheet PDF文件第3页浏览型号CY7C027V-25AI的Datasheet PDF文件第4页浏览型号CY7C027V-25AI的Datasheet PDF文件第5页浏览型号CY7C027V-25AI的Datasheet PDF文件第6页浏览型号CY7C027V-25AI的Datasheet PDF文件第7页 
CY7C027V/027AV/028V  
CY7C037AV/038V  
3.3 V 32K/64K x 16/18 Dual-Port Static  
RAM  
Fully asynchronous operation  
Automatic power-down  
Features  
True dual-ported memory cells which allow  
simultaneous access of the same memory location  
Expandable data bus to 32/36 bits or more using Master/Slave  
chip select when using more than one device  
32K x 16 organization (CY7C027V/027AV [1]  
64K x 16 organization (CY7C028V)  
32K x 18 organization (CY7C037AV)  
64K x 18 organization (CY7C038V)  
)
On-chip arbitration logic  
Semaphores included to permit software handshaking  
between ports  
INT flag for port-to-port communication  
0.35 micron Complementary metal oxide semiconductor  
(CMOS) for optimum speed and power  
Separate upper-byte and lower-byte control  
Dual chip enables  
High speed access: 15, 20, and 25 ns  
Low operating power  
Pin select for Master or Slave  
Commercial and Industrial temperature ranges  
Active: ICC = 115 mA (typical)  
Standby: ISB3 = 10 A (typical)  
100-pin Pb-free Thin quad plastic flatpack (TQFP) and 100-pin  
TQFP  
Logic Block Diagram  
R/W  
R/W  
UB  
L
R
R
UB  
L
CE  
CE  
CE  
CE  
0L  
1L  
0R  
1R  
CE  
CE  
R
L
LB  
LB  
R
L
L
OE  
OE  
R
8/9  
8/9  
[2]  
15/17L  
[3]  
I/O  
–I/O  
I/O  
–I/O [2]  
8/9L  
8/9L  
15/17R  
[3]  
8/9  
8/9  
I/O  
Control  
I/O  
Control  
I/O –I/O  
I/O –I/O  
0L  
7/8L  
0L  
7/8R  
15/16  
15/16  
[4]  
A
A
–A[4]  
A
A
–A  
Address  
Decode  
Address  
Decode  
True Dual-Ported  
0L  
14/15L  
0R  
14/15R  
14/15R  
RAM Array  
15/16  
15/16  
–A[4]  
[4]  
–A  
0L  
14/15L  
0R  
CE  
CE  
R
Interrupt  
Semaphore  
Arbitration  
L
OE  
OE  
R
L
R/W  
SEM  
R/W  
SEM  
L
R
R
L
[5]  
[5]  
BUSY  
INT  
UB  
BUSY  
INT  
UB  
L
R
R
R
R
L
L
LB  
M/S  
LB  
L
Notes  
1. CY7C027V, and CY7C027AV are functionally identical.  
2. I/O –I/O for x16 devices; I/O –I/O for x18 devices.  
8
15  
9
17  
3. I/O –I/O for x16 devices; I/O –I/O for x18 devices.  
0
7
0
8
4. A –A for 32K; A –A for 64K devices.  
0
14  
0
15  
5. BUSY is an output in master mode and an input in slave mode.  
Cypress Semiconductor Corporation  
Document #: 38-06078 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised October 14, 2011  

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