Datasheet > CY7C027V

CY7C027V

更新时间： 2024-09-17 00:01:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
18页	237K
描述
3.3V 32K/64K x 16/18 Dual-Port Static RAM

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中文翻译

获取价格

数据手册

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CY7C027V 数据手册

CY7C027V/028V

CY7C037V/038V

LEAD-FREE

3.3V 32K/64K x 16/18 Dual-Port Static RAM

• Fully asynchronous operation

• Automatic power-down

• Expandable data bus to 32/36 bits or more using Mas-

ter/Slave chip select when using more than one device

Features

• True Dual-Ported memory cells which allow

simultaneous access of the same memory location

• 32K x 16 organization (CY7C027V)

• 64K x 16 organization (CY7C028V)

• 32K x 18 organization (CY7C037V)

• 64K x 18 organization (CY7C038V)

• 0.35-micron CMOS for optimum speed/power

• High-speed access: 15/20/25 ns

• Low operating power

• On-chip arbitration logic

• Semaphores included to permit software handshaking

between ports

• INT flag for port-to-port communication

• Separate upper-byte and lower-byte control

• Dual Chip Enables

• Pin select for Master or Slave

— Active: I_CC= 115 mA (typical)

• Commercial and Industrial temperature ranges

• 100-pin Lead(Pb)-free TQFP and 100-pin TQFP

—Standby: I_SB3= 10 µA (typical)

Logic Block Diagram

R/W

8/9

[1]

I/O

–I/O

[2]

I/O

–I/O

8/9L

15/17L

8/9L

15/17R

[2]

8/9

I/O

Control

I/O

Control

I/O –I/O

7/8L

7/8R

15/16

[3]

–A

–A^[3]

Address

Decode

Address

Decode

True Dual-Ported

0L 14/15L

14/15R

RAM Array

15/16

–A^[3]

[3]

–A

0L 14/15L

14/15R

Interrupt

Semaphore

Arbitration

R/W

SEM

[4]

BUSY

INT

M/S

Notes:

1. I/O –I/O for x16 devices; I/O –I/O for x18 devices.

2. I/O –I/O for x16 devices; I/O –I/O for x18 devices.

3. A –A for 32K; A –A for 64K devices.

4. BUSY is an output in master mode and an input in slave mode.

Cypress Semiconductor Corporation

Document #: 38-06078 Rev. *A

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised September 20, 2004

12 3 4 5 6 7...18

中文翻译

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