25/0251
CY7C027/028
CY7C037/038
32K/64K x 16/18
Dual-Port Static RAM
• Fully asynchronous operation
Features
• Automatic power-down
• Expandable data bus to 32/36 bits or more using Mas-
ter/Slave chip select when using more than one device
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• 32K x 16 organization (CY7C027)
• 64K x 16 organization (CY7C028)
• 32K x 18 organization (CY7C037)
• 64K x 18 organization (CY7C038)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 12[1]/15/20 ns
• Low operating power
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flags for port-to-port communication
• Separate upper-byte and lower-byte control
• Dual Chip Enables
• Pin select for Master or Slave
— Active: ICC = 180 mA (typical)
• Commercial and industrial temperature ranges
• Available in 100-pin TQFP
— Standby: ISB3 = 0.05 mA (typical)
• Pin-compatible and functionally equivalent to IDT7027
Logic Block Diagram
R/WL
UBL
R/WR
UBR
CE0L
CE0R
CE1L
CE1R
CEL
CER
LBL
LBR
OEL
OER
8/9
[2]
8/9
8/9
[2]
I/O8/9L–I/O15/17L
I/O8/9L–I/O15/17R
8/9
[3]
[3]
I/O
Control
I/O
Control
I/O0L–I/O7/8L
I/O0L–I/O7/8R
15/16
[4]
15/16
[4]
Address
Decode
Address
Decode
True Dual-Ported
A0L–A
A
0R–A14/15R
14/15L
RAM Array
15/16
15/16
[4]
[4]
A0L–A
A0R–A14/15R
14/15L
CEL
CER
Interrupt
Semaphore
Arbitration
OEL
OER
R/WL
SEML
BUSYL[5]
R/WR
SEMR
[5] BUSYR
INTR
INTL
UBL
UBR
LBL
M/S
LBR
Notes:
1. See page 6 for Load Conditions.
2. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.
3. I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices.
4. A0–A14 for 32K; A0–A15 for 64K devices.
5. BUSY is an output in master mode and an input in slave mode.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-06042 Rev. *A
Revised December 27, 2002