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CY7C027V_13 PDF预览

CY7C027V_13

更新时间: 2024-11-07 12:28:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
24页 641K
描述
3.3 V 32 K / 64 K × 16 / 18 Dual-Port Static RAM

CY7C027V_13 数据手册

 浏览型号CY7C027V_13的Datasheet PDF文件第2页浏览型号CY7C027V_13的Datasheet PDF文件第3页浏览型号CY7C027V_13的Datasheet PDF文件第4页浏览型号CY7C027V_13的Datasheet PDF文件第5页浏览型号CY7C027V_13的Datasheet PDF文件第6页浏览型号CY7C027V_13的Datasheet PDF文件第7页 
CY7C027V/027AV/028V  
CY7C037AV/038V  
3.3 V 32 K / 64 K × 16 / 18 Dual-Port  
Static RAM  
3.3  
V 32 K / 64 K × 16 / 18 Dual-Port Static RAM  
Fully asynchronous operation  
Automatic power-down  
Features  
True dual-ported memory cells which allow simultaneous  
access of the same memory location  
Expandable data bus to 32/36 bits or more using Master/Slave  
chip select when using more than one device  
32K x 16 organization (CY7C027V/027AV [1]  
64K x 16 organization (CY7C028V)  
32K x 18 organization (CY7C037AV)  
64K x 18 organization (CY7C038V)  
)
On-chip arbitration logic  
Semaphores included to permit software handshaking  
between ports  
INT flag for port-to-port communication  
Separate upper-byte and lower-byte control  
Dual chip enables  
0.35 micron Complementary metal oxide semiconductor  
(CMOS) for optimum speed and power  
High speed access: 15, 20, and 25 ns  
Low operating power  
Pin select for Master or Slave  
Commercial and Industrial temperature ranges  
Active: ICC = 115 mA (typical)  
Standby: ISB3 = 10 A (typical)  
100-pin Pb-free Thin quad plastic flatpack (TQFP) and 100-pin  
TQFP  
Logic Block Diagram  
R/W  
R/W  
UB  
L
R
R
UB  
L
CE  
CE  
CE  
CE  
0L  
1L  
0R  
1R  
CE  
CE  
R
L
LB  
LB  
R
L
L
OE  
OE  
R
8/9  
8/9  
[2]  
15/17L  
[3]  
I/O  
–I/O  
I/O  
–I/O [2]  
8/9L  
8/9L  
15/17R  
[3]  
8/9  
8/9  
I/O  
Control  
I/O  
Control  
I/O –I/O  
I/O –I/O  
0L  
7/8L  
0L  
7/8R  
15/16  
15/16  
[4]  
A
A
–A[4]  
A
A
–A  
Address  
Decode  
Address  
Decode  
True Dual-Ported  
0L  
14/15L  
0R  
14/15R  
14/15R  
RAM Array  
15/16  
15/16  
–A[4]  
[4]  
–A  
0L  
14/15L  
0R  
CE  
CE  
R
Interrupt  
Semaphore  
Arbitration  
L
OE  
OE  
R
L
R/W  
SEM  
R/W  
SEM  
L
R
R
L
[5]  
[5]  
BUSY  
INT  
UB  
BUSY  
INT  
UB  
L
R
R
R
R
L
L
LB  
M/S  
LB  
L
Notes  
1. CY7C027V, and CY7C027AV are functionally identical.  
2. I/O –I/O for x16 devices; I/O –I/O for x18 devices.  
8
15  
9
17  
3. I/O –I/O for x16 devices; I/O –I/O for x18 devices.  
0
7
0
8
4. A –A for 32K; A –A for 64K devices.  
0
14  
0
15  
5. BUSY is an output in master mode and an input in slave mode.  
Cypress Semiconductor Corporation  
Document Number: 38-06078 Rev. *G  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised February 5, 2013  

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