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CY7C027VN-15AXC PDF预览

CY7C027VN-15AXC

更新时间: 2024-11-09 06:51:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
18页 456K
描述
3.3V 32K/64K x 16/18 Dual-Port Static RAM

CY7C027VN-15AXC 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:QFP包装说明:LFQFP,
针数:100Reach Compliance Code:unknown
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:5.77Is Samacsys:N
最长访问时间:15 nsJESD-30 代码:S-PQFP-G100
长度:14 mm内存密度:524288 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端子数量:100字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32KX16封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:14 mm
Base Number Matches:1

CY7C027VN-15AXC 数据手册

 浏览型号CY7C027VN-15AXC的Datasheet PDF文件第2页浏览型号CY7C027VN-15AXC的Datasheet PDF文件第3页浏览型号CY7C027VN-15AXC的Datasheet PDF文件第4页浏览型号CY7C027VN-15AXC的Datasheet PDF文件第5页浏览型号CY7C027VN-15AXC的Datasheet PDF文件第6页浏览型号CY7C027VN-15AXC的Datasheet PDF文件第7页 
CY7C027V/027VN/027AV/028V  
CY7C037V/037AV/038V  
3.3V 32K/64K x 16/18 Dual-Port Static  
RAM  
Fully asynchronous operation  
Automatic power down  
Features  
True Dual-Ported memory cells which allow  
Expandable data bus to 32/36 bits or more using Master/Slave  
chip select when using more than one device  
simultaneous access of the same memory location  
32K x 16 organization (CY7C027V/027VN/027AV [1]  
)
On-chip arbitration logic  
64K x 16 organization (CY7C028V)  
Semaphores included to permit software handshaking  
between ports  
32K x 18 organization (CY7C037V/037AV[2]  
64K x 18 organization (CY7C038V)  
)
INT flag for port-to-port communication  
Separate upper-byte and lower-byte control  
Dual chip enables  
0.35 micron CMOS for optimum speed and power  
High speed access: 15, 20, and 25 ns  
Low operating power  
Pin select for Master or Slave  
Active: ICC = 115 mA (typical)  
Commercial and Industrial temperature ranges  
100-pin Pb-free TQFP and 100-pin TQFP  
Standby: ISB3 = 10 μA (typical)  
Logic Block Diagram  
R/W  
R/W  
UB  
L
R
R
UB  
L
CE  
CE  
CE  
CE  
0L  
1L  
0R  
1R  
CE  
CE  
R
L
LB  
LB  
R
L
L
OE  
OE  
R
8/9  
8/9  
[3]  
15/17L  
[4]  
I/O  
–I/O  
I/O  
–I/O[3]  
8/9L  
8/9L  
15/17R  
[4]  
8/9  
8/9  
I/O  
Control  
I/O  
Control  
I/O –I/O  
I/O –I/O  
0L  
7/8L  
0L  
7/8R  
15/16  
15/16  
[5]  
A
A
–A[5]  
A
A
–A  
Address  
Decode  
Address  
Decode  
True Dual-Ported  
0L  
14/15L  
0R  
14/15R  
14/15R  
RAM Array  
15/16  
15/16  
–A[5]  
[5]  
–A  
0L  
14/15L  
0R  
CE  
CE  
R
Interrupt  
Semaphore  
Arbitration  
L
OE  
OE  
R
L
R/W  
SEM  
R/W  
SEM  
L
R
R
L
[6]  
[6]  
BUSY  
INT  
BUSY  
INT  
UB  
L
R
R
R
R
L
UB  
L
LB  
M/S  
LB  
L
Notes  
1. CY7C027V, CY7C027VN and CY7C027AV are functionally identical.  
2. CY7C037V and CY7C037AV are functionally identical.  
3. I/O –I/O for x16 devices; I/O –I/O for x18 devices.  
8
15  
9
17  
4. I/O –I/O for x16 devices; I/O –I/O for x18 devices.  
0
7
0
8
5. A –A for 32K; A –A for 64K devices.  
0
14  
0
15  
6. BUSY is an output in master mode and an input in slave mode.  
Cypress Semiconductor Corporation  
Document #: 38-06078 Rev. *B  
198 Champion Court  
San Jose  
,
CA 95134-1709  
408-943-2600  
Revised December 09, 2008  
[+] Feedback  

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