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CY7C027-12AC PDF预览

CY7C027-12AC

更新时间: 2024-09-16 22:06:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
19页 258K
描述
32K/64K x 16/18 Dual-Port Static RAM

CY7C027-12AC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, TQFP-100
针数:100Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
Factory Lead Time:1 week风险等级:5.51
最长访问时间:12 ns其他特性:INTERRUPT FLAG
I/O 类型:COMMONJESD-30 代码:S-PQFP-G100
JESD-609代码:e0长度:14 mm
内存密度:524288 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:16湿度敏感等级:3
功能数量:1端口数量:2
端子数量:100字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32KX16输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP100,.63SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:5 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.0015 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.325 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

CY7C027-12AC 数据手册

 浏览型号CY7C027-12AC的Datasheet PDF文件第2页浏览型号CY7C027-12AC的Datasheet PDF文件第3页浏览型号CY7C027-12AC的Datasheet PDF文件第4页浏览型号CY7C027-12AC的Datasheet PDF文件第5页浏览型号CY7C027-12AC的Datasheet PDF文件第6页浏览型号CY7C027-12AC的Datasheet PDF文件第7页 
25/0251  
CY7C027/028  
CY7C037/038  
32K/64K x 16/18  
Dual-Port Static RAM  
Fully asynchronous operation  
Features  
Automatic power-down  
Expandable data bus to 32/36 bits or more using Mas-  
ter/Slave chip select when using more than one device  
• True Dual-Ported memory cells which allow simulta-  
neous access of the same memory location  
• 32K x 16 organization (CY7C027)  
• 64K x 16 organization (CY7C028)  
• 32K x 18 organization (CY7C037)  
• 64K x 18 organization (CY7C038)  
• 0.35-micron CMOS for optimum speed/power  
• High-speed access: 12[1]/15/20 ns  
• Low operating power  
On-chip arbitration logic  
Semaphores included to permit software handshaking  
between ports  
INT flags for port-to-port communication  
Separate upper-byte and lower-byte control  
Dual Chip Enables  
Pin select for Master or Slave  
Active: ICC = 180 mA (typical)  
Commercial and industrial temperature ranges  
Available in 100-pin TQFP  
Standby: ISB3 = 0.05 mA (typical)  
Pin-compatible and functionally equivalent to IDT7027  
Logic Block Diagram  
R/WL  
UBL  
R/WR  
UBR  
CE0L  
CE0R  
CE1L  
CE1R  
CEL  
CER  
LBL  
LBR  
OEL  
OER  
8/9  
[2]  
8/9  
8/9  
[2]  
I/O8/9LI/O15/17L  
I/O8/9LI/O15/17R  
8/9  
[3]  
[3]  
I/O  
Control  
I/O  
Control  
I/O0LI/O7/8L  
I/O0LI/O7/8R  
15/16  
[4]  
15/16  
[4]  
Address  
Decode  
Address  
Decode  
True Dual-Ported  
A0LA  
A
0RA14/15R  
14/15L  
RAM Array  
15/16  
15/16  
[4]  
[4]  
A0LA  
A0RA14/15R  
14/15L  
CEL  
CER  
Interrupt  
Semaphore  
Arbitration  
OEL  
OER  
R/WL  
SEML  
BUSYL[5]  
R/WR  
SEMR  
[5] BUSYR  
INTR  
INTL  
UBL  
UBR  
LBL  
M/S  
LBR  
Notes:  
1. See page 6 for Load Conditions.  
2. I/O8I/O15 for x16 devices; I/O9I/O17 for x18 devices.  
3. I/O0I/O7 for x16 devices; I/O0I/O8 for x18 devices.  
4. A0A14 for 32K; A0A15 for 64K devices.  
5. BUSY is an output in master mode and an input in slave mode.  
For the most recent information, visit the Cypress web site at www.cypress.com  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-06042 Rev. *A  
Revised December 27, 2002  

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