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CY7C027-20AXCT PDF预览

CY7C027-20AXCT

更新时间: 2024-11-09 21:14:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
19页 323K
描述
Multi-Port SRAM, 32KX16, 20ns, CMOS, PQFP100, ROHS COMPLIANT, PLASTIC, MS-026, TQFP-100

CY7C027-20AXCT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:ROHS COMPLIANT, PLASTIC, MS-026, TQFP-100
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.82
最长访问时间:20 ns其他特性:FLOW-THROUGH
I/O 类型:COMMONJESD-30 代码:S-PQFP-G100
JESD-609代码:e4长度:14 mm
内存密度:524288 bit内存集成电路类型:MULTI-PORT SRAM
内存宽度:16湿度敏感等级:3
功能数量:1端口数量:2
端子数量:100字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.0015 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.265 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

CY7C027-20AXCT 数据手册

 浏览型号CY7C027-20AXCT的Datasheet PDF文件第2页浏览型号CY7C027-20AXCT的Datasheet PDF文件第3页浏览型号CY7C027-20AXCT的Datasheet PDF文件第4页浏览型号CY7C027-20AXCT的Datasheet PDF文件第5页浏览型号CY7C027-20AXCT的Datasheet PDF文件第6页浏览型号CY7C027-20AXCT的Datasheet PDF文件第7页 
CY7C027/028  
CY7C037/03832K/64K  
x 16/18 Dual-Port Static RAM  
CY7C027/028  
CY7C037/038  
32K/64K x 16/18 Dual-Port Static RAM  
Automatic power down  
Features  
Expandable data bus to 32 and 36 bits or more using  
Master/Slave chip select when using more than one device  
On-chip arbitration logic  
Semaphores included to permit software handshaking  
between ports  
INT flags for port-to-port communication  
Separate upper-byte and lower-byte control  
Dual chip enables  
True dual-ported memory cells which allow simultaneous  
access of the same memory location  
32K x 16 organization (CY7C027)  
64K x 16 organization (CY7C028)  
32K x 18 organization (CY7C037)  
64K x 18 organization (CY7C038)  
0.35 micron CMOS for optimum speed and power  
High speed access: 12[1], 15, and 20 ns  
Low operating power  
Pin select for Master or Slave  
Commercial and industrial temperature ranges  
Available in 100-pin TQFP  
Active: ICC = 180 mA (typical)  
Standby: ISB3 = 0.05 mA (typical)  
Fully asynchronous operation  
Pb-free packages available  
Logic Block Diagram  
R/WL  
UBL  
R/WR  
UBR  
CE0L  
CE0R  
CE1L  
CE1R  
CEL  
CER  
LBL  
LBR  
OEL  
OER  
8/9  
[2]  
8/9  
[2]  
I/O8/9L–I/O15/17L  
I/O8/9L–I/O15/17R  
8/9  
8/9  
I/O  
Control  
I/O  
Control  
[3]  
[3]  
I/O0L–I/O7/8L  
I/O0L–I/O7/8R  
15/16  
15/16  
Address  
Decode  
Address  
Decode  
True Dual-Ported  
RAM Array  
[4]  
[4]  
A0L–A14/15L  
A0R–A14/15R  
15/16  
15/16  
[4]  
[4]  
A0L–A14/15L  
A0R–A14/15R  
CEL  
CER  
OER  
Interrupt  
Semaphore  
Arbitration  
OEL  
R/WL  
SEML  
R/WR  
SEMR  
[5]  
[5]  
BUSYL  
BUSYR  
INTL  
UBL  
LBL  
INTR  
UBR  
LBR  
M/S  
Notes  
1. See page 6 for Load Conditions.  
2. I/O –I/O for x16 devices; I/O –I/O for x18 devices.  
8
15  
9
17  
3. I/O –I/O for x16 devices; I/O –I/O for x18 devices.  
0
7
0
8
4. A –A for 32K; A –A for 64K devices.  
0
14  
0
15  
5. BUSY is an output in master mode and an input in slave mode.  
Cypress Semiconductor Corporation  
Document #: 38-06042 Rev. *D  
198 Champion Court  
San Jose  
,
CA 95134-1709  
408-943-2600  
Revised December 10, 2008  
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