CY62167DV20
MoBL2™
16-Mb (1024K x 16) Static RAM
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected Chip
Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW or both
BHE and BLE are HIGH. The input/output pins (I/O0 through
I/O15) are placed in a high-impedance state when: deselected
Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW,
outputs are disabled (OE HIGH), both Byte High Enable and
Byte Low Enable are disabled (BHE, BLE HIGH) or during a
write operation (Chip Enable 1 (CE1) LOW and Chip Enable 2
(CE2) HIGH and WE LOW).
Features
• Very high speed: 55 ns and 70 ns
• Wide voltage range: 1.65V to 2.2V
• Ultra-low active power
—Typical active current: 1.5 mA @ f = 1 MHz
—Typical active current: 18 mA @ f = fMAX
• Ultra-low standby power
• Easy memory expansion with CE1, CE2, and OE
features
• Automatic power-down when deselected
• CMOS for optimum speed/power
Writing to the device is accomplished by taking Chip Enable 1
(CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then das
pins (A0 through A19). If Byte High Enable (BHE) is LOW, then
data from I/O pins (I/O8 through I/O15) is written into the
location specified on the ad
• Packages offered in a 48-ball FBGA
Functional Description[1]
Reading from the device is accomplished by taking Chip
Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and
Output Enable (OE) LOW while forcing the Write Enable (WE)
HIGH. If Byte Low Enable (<>O7. If Byte High Enable (BHE)
is LOW, then data from memory will appear on I/O8 to I/O15.
See the truth table at the back of this data sheet for a complete
description of read and write modes.
The CY62167DV20 is a high-performance CMOS static RAM
organized as 1024K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery LifeTM (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
DATA IN DRIVERS
Logic Block Diagram
A10
A 9
A 8
A 7
A 6
A 5
A 4
A 3
A 2
1024K x 16
RAM ARRAY
2048 x 512 x 16
I/O0–I/O7
I/O8–I/O15
A 1
A 0
COLUMN DECODER
BHE
WE
CE2
CE
1
OE
BLE
Power-down
Circuit
CE2
CE1
BHE
BLE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress SemiconductorCorporation
Document #: 38-05327 Rev. *B
•
3901 North First Street
•
SanJose, CA 95134
•
408-943-2600
Revised January 2, 2004