5秒后页面跳转
捷配首页

Datasheet > 存储 > SRAM> CY62167DV30LL-55ZIT
CY62167DV30LL-55ZIT PDF预览

CY62167DV30LL-55ZIT

更新时间： 2024-11-20 13:07:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 343K
描述
Standard SRAM, 1MX16, 55ns, CMOS, PDSO48, 12 X 18.40 MM, 1 MM HEIGHT, MO-142, TSOP1-48

阅读下载

中文翻译

获取价格

CY62167DV30LL-55ZIT 技术参数

生命周期：Obsolete零件包装代码：TSOP1
包装说明：TSOP1,针数：48
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41Factory Lead Time：1 week
风险等级：5.75Is Samacsys：N
最长访问时间：55 ns其他特性：CONFIGURABLE AS 2M X 8 ALSO
JESD-30 代码：R-PDSO-G48JESD-609代码：e0
长度：18.4 mm内存密度：16777216 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
功能数量：1端子数量：48
字数：1048576 words字数代码：1000000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：1MX16
封装主体材料：PLASTIC/EPOXY封装代码：TSOP1
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.2 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL宽度：12 mm
Base Number Matches：1

CY62167DV30LL-55ZIT 数据手册

 浏览型号CY62167DV30LL-55ZIT的Datasheet PDF文件第2页浏览型号CY62167DV30LL-55ZIT的Datasheet PDF文件第3页浏览型号CY62167DV30LL-55ZIT的Datasheet PDF文件第4页浏览型号CY62167DV30LL-55ZIT的Datasheet PDF文件第5页浏览型号CY62167DV30LL-55ZIT的Datasheet PDF文件第6页浏览型号CY62167DV30LL-55ZIT的Datasheet PDF文件第7页 
CY62167DV30 MoBL®  
16-Mbit (1M x 16) Static RAM  
also has an automatic power-down feature that significantly  
reduces power consumption by 99% when addresses are not  
toggling. The device can also be put into standby mode when  
deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are  
HIGH). The input/output pins (I/O0 through I/O15) are placed  
in a high-impedance state when: deselected (CE1HIGH or CE2  
LOW), outputs are disabled (OE HIGH), both Byte High  
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),  
or during a Write operation (CE1 LOW, CE2 HIGH and WE  
LOW).  
Features  
• TSOP I Configurable as 1M x 16 or as 2M x 8 SRAM  
• Very high speed: 45 ns  
• Wide voltage range: 2.2V – 3.6V  
• Ultra-low active power  
— Typical active current: 2 mA @ f = 1 MHz  
— Typical active current: 18.5 mA @ f = fMax (45 ns  
speed)  
Writing to the device is accomplished by taking Chip Enables  
(CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW.  
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0  
through I/O7), is written into the location specified on the  
address pins (A0 through A19). If Byte High Enable (BHE) is  
LOW, then data from I/O pins (I/O8 through I/O15) is written into  
the location specified on the address pins (A0 through A19).  
• Ultra-low standby power  
• Easy memory expansion with CE1, CE2 and OE features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Available in Pb-free and non Pb-free 48-ball VFBGA  
and 48-pin TSOP I package  
Reading from the device is accomplished by taking Chip  
Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE)  
LOW while forcing the Write Enable (WE) HIGH. If Byte Low  
Enable (BLE) is LOW, then data from the memory location  
specified by the address pins will appear on I/O0 to I/O7. If Byte  
High Enable (BHE) is LOW, then data from memory will appear  
on I/O8 to I/O15. See the truth table at the back of this data  
sheet for a complete description of Read and Write modes.  
Functional Description[1]  
The CY62167DV30 is a high-performance CMOS static RAM  
organized as 1M words by 16 bits. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones. The device  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A 9  
A 8  
A 7  
A 6  
A 5  
A 4  
A 3  
1M × 16 / 2M x 8  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
A 2  
A 1  
A 0  
COLUMN DECODER  
BYTE  
BHE  
WE  
CE2  
CE1  
OE  
BLE  
Power-Down  
Circuit  
CE2  
CE1  
BHE  
BLE  
Note:  
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05328 Rev. *G  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised July 27, 2006  
[+] Feedback  
1234567...12

中文翻译

下载PDF

与CY62167DV30LL-55ZIT相关器件

型号 品牌 获取价格 描述 数据表
CY62167DV30LL-55ZXI CYPRESS

获取价格

 		16-Mbit (1M x 16) Static RAM
CY62167DV30LL-55ZXI INFINEON

获取价格

 		Asynchronous SRAM
CY62167DV30LL-55ZXIT INFINEON

获取价格

 		Asynchronous SRAM
CY62167DV30LL-70BVI CYPRESS

获取价格

 		16-Mbit (1M x 16) Static RAM
CY62167DV30LL-70BVI INFINEON

获取价格

 		Asynchronous SRAM
CY62167DV30LL-70BVIT INFINEON

获取价格

 		Asynchronous SRAM
CY62167DV30LL-70BVXIT CYPRESS

获取价格

 		Standard SRAM, 1MX16, 70ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62167DV30LL-70ZI ROCHESTER

获取价格

 		1MX16 STANDARD SRAM, 70ns, PDSO48, 12 X 18.40 MM, 1 MM HEIGHT, TSOP1-48
CY62167DV30LL-70ZI CYPRESS

获取价格

 		16-Mbit (1M x 16) Static RAM
CY62167DV30LL-70ZIT CYPRESS

获取价格

 		Standard SRAM, 1MX16, 70ns, CMOS, PDSO48, 12 X 18.40 MM, 1 MM HEIGHT, TSOP1-48

与CY62167DV30LL-55ZIT相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证