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CY62167DV20LL-70BVI PDF预览

CY62167DV20LL-70BVI

更新时间： 2024-11-20 09:42:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
10页 244K
描述
16-Mb (1024K x 16) Static RAM

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中文翻译

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CY62167DV20LL-70BVI 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：BGA包装说明：VFBGA, BGA48,6X8,30
针数：48Reach Compliance Code：not_compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.88Is Samacsys：N
最长访问时间：70 nsI/O 类型：COMMON
JESD-30 代码：R-PBGA-B48JESD-609代码：e0
长度：9.5 mm内存密度：16777216 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
功能数量：1端子数量：48
字数：1048576 words字数代码：1000000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：1MX16
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装等效代码：BGA48,6X8,30
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行：PARALLEL电源：1.8/2 V
认证状态：Not Qualified座面最大高度：1 mm
最小待机电流：1 V子类别：SRAMs
最大压摆率：0.03 mA最大供电电压 (Vsup)：2.2 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：0.75 mm
端子位置：BOTTOM宽度：8 mm
Base Number Matches：1

CY62167DV20LL-70BVI 数据手册

 浏览型号CY62167DV20LL-70BVI的Datasheet PDF文件第2页浏览型号CY62167DV20LL-70BVI的Datasheet PDF文件第3页浏览型号CY62167DV20LL-70BVI的Datasheet PDF文件第4页浏览型号CY62167DV20LL-70BVI的Datasheet PDF文件第5页浏览型号CY62167DV20LL-70BVI的Datasheet PDF文件第6页浏览型号CY62167DV20LL-70BVI的Datasheet PDF文件第7页 
CY62167DV20  
MoBL2™  
16-Mb (1024K x 16) Static RAM  
toggling. The device can be put into standby mode reducing  
power consumption by more than 99% when deselected Chip  
Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW or both  
BHE and BLE are HIGH. The input/output pins (I/O0 through  
I/O15) are placed in a high-impedance state when: deselected  
Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW,  
outputs are disabled (OE HIGH), both Byte High Enable and  
Byte Low Enable are disabled (BHE, BLE HIGH) or during a  
write operation (Chip Enable 1 (CE1) LOW and Chip Enable 2  
(CE2) HIGH and WE LOW).  
Features  
• Very high speed: 55 ns and 70 ns  
• Wide voltage range: 1.65V to 2.2V  
• Ultra-low active power  
—Typical active current: 1.5 mA @ f = 1 MHz  
—Typical active current: 18 mA @ f = fMAX  
• Ultra-low standby power  
• Easy memory expansion with CE1, CE2, and OE  
features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
Writing to the device is accomplished by taking Chip Enable 1  
(CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable  
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then das  
pins (A0 through A19). If Byte High Enable (BHE) is LOW, then  
data from I/O pins (I/O8 through I/O15) is written into the  
location specified on the ad  
• Packages offered in a 48-ball FBGA  
Functional Description[1]  
Reading from the device is accomplished by taking Chip  
Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and  
Output Enable (OE) LOW while forcing the Write Enable (WE)  
HIGH. If Byte Low Enable (<>O7. If Byte High Enable (BHE)  
is LOW, then data from memory will appear on I/O8 to I/O15.  
See the truth table at the back of this data sheet for a complete  
description of read and write modes.  
The CY62167DV20 is a high-performance CMOS static RAM  
organized as 1024K words by 16 bits. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery LifeTM (MoBL®) in  
portable applications such as cellular telephones. The device  
also has an automatic power-down feature that significantly  
reduces power consumption by 99% when addresses are not  
DATA IN DRIVERS  
Logic Block Diagram  
A10  
A 9  
A 8  
A 7  
A 6  
A 5  
A 4  
A 3  
A 2  
1024K x 16  
RAM ARRAY  
2048 x 512 x 16  
I/O0–I/O7  
I/O8–I/O15  
A 1  
A 0  
COLUMN DECODER  
BHE  
WE  
CE2  
CE  
1
OE  
BLE  
Power-down  
Circuit  
CE2  
CE1  
BHE  
BLE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress SemiconductorCorporation  
Document #: 38-05327 Rev. *B  
•
3901 North First Street  
•
SanJose, CA 95134  
•
408-943-2600  
Revised January 2, 2004  
1234567...10

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