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CY62167DV18LL-55BVXI

更新时间： 2024-01-07 16:17:02
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
11页 544K
描述
16-Mbit (1M x 16) Static RAM

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中文翻译

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CY62167DV18LL-55BVXI 技术参数

生命周期：Obsolete零件包装代码：BGA
包装说明：VFBGA,针数：48
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.71
最长访问时间：55 nsJESD-30 代码：R-PBGA-B48
长度：9.5 mm内存密度：16777216 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
功能数量：1端子数量：48
字数：1048576 words字数代码：1000000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：1MX16
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：1 mm最大供电电压 (Vsup)：1.95 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：0.75 mm端子位置：BOTTOM
宽度：8 mmBase Number Matches：1

CY62167DV18LL-55BVXI 数据手册

 浏览型号CY62167DV18LL-55BVXI的Datasheet PDF文件第2页浏览型号CY62167DV18LL-55BVXI的Datasheet PDF文件第3页浏览型号CY62167DV18LL-55BVXI的Datasheet PDF文件第4页浏览型号CY62167DV18LL-55BVXI的Datasheet PDF文件第5页浏览型号CY62167DV18LL-55BVXI的Datasheet PDF文件第6页浏览型号CY62167DV18LL-55BVXI的Datasheet PDF文件第7页 
CY62167DV18 MoBL®  
16-Mbit (1M x 16) Static RAM  
consumption by more than 99% when deselected (CE1 HIGH  
or CE2 LOW or both BHE and BLE are HIGH). The input and  
output pins (IO0 through IO15) are placed in a high impedance  
state when:  
Features  
• Very high speed: 55 ns  
• Wide voltage range: 1.65V–1.95V  
• Ultra low active power  
• Deselected (CE1 HIGH or CE2 LOW)  
• Outputs are disabled (OE HIGH)  
— Typical active current: 1.5 mA @ f = 1 MHz  
— Typical active current: 15 mA @ f = fmax  
• Ultra low standby power  
• Both Byte High Enable (BHE) and Byte Low Enable (BLE)  
are disabled (BHE, BLE HIGH)  
• Write operation is active (CE1 LOW, CE2 HIGH and WE  
LOW)  
• Easy memory expansion with CE1, CE2, and OE features  
• Automatic power down when deselected  
• CMOS for optimum speed and power  
• Available in Pb-free 48-ball VFBGA package  
To write to the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Write Enable (WE) input LOW. If BLE is LOW, then  
data from IO pins (IO0 through IO7) is written into the location  
specified on the address pins (A0 through A19). If BHE is LOW  
then data from IO pins (IO8 through IO15) is written into the  
location specified on the address pins (A0 through A19).  
Functional Description[1]  
The CY62167DV18 is a high performance CMOS static RAM  
organized as 1M words by 16 bits. This device features  
advanced circuit design to provide ultra low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones. The device  
also has an automatic power down feature that significantly  
reduces power consumption by 99% when addresses are not  
toggling. Placing the device into standby mode reduces power  
To read from the device, take Chip Enables (CE1 LOW and  
CE2 HIGH) and OE LOW while forcing the WE HIGH. If BLE  
is LOW, then data from the memory location specified by the  
address pins appear on IO0 to IO7. If BHE is LOW, then data  
from memory appears on IO8 to IO15. See the “Truth Table” on  
page 9 for a complete description of read and write modes.  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A 9  
A 8  
A 7  
A 6  
A 5  
A 4  
A 3  
1M × 16  
RAM Array  
IO0–IO7  
IO8–IO15  
A 2  
A 1  
A 0  
COLUMN DECODER  
BYTE  
BHE  
WE  
CE2  
CE1  
OE  
PowerDown  
Circuit  
BLE  
CE2  
CE1  
BHE  
BLE  
Note  
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05326 Rev. *C  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised April 25, 2007  
1234567...11

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