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CY2CC1910

更新时间： 2024-11-24 22:10:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
8页	131K
描述
1:10 Clock Fanout Buffer with Output Enable

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CY2CC1910 数据手册

COMLINK™ SERIES

CY2CC1910

1:10 Clock Fanout Buffer with Output Enable

Features

Description

• Low-voltage operation

• Full-range support:

— 3.3V

— 2.5V

— 1.8V

The Cypress series of network circuits are produced using

advanced 0.35-micron CMOS technology, achieving the

industries fastest logic and buffers.

The Cypress CY2CC1910 fanout buffer features one input and

ten outputs. Ideal for conversion from/to 3.3V/2.5V/1.8V.

Designed for data communications clock management appli-

cations, the large fanout from a single input reduces loading

on the input clock.

Cypress employs unique AVCMOS-type outputs VOI™

(Variable Output Impedance) that dynamically adjust for

variable impedance matching and eliminate the need for

series damping resistors; they also reduce noise overall.

• 1:10 fanout

• Drives either a 50-Ohm or 75-Ohm load

• Over voltage tolerant input hot swappable

• Low-input capacitance

• Low-output skew

• Low-propagation delay

• Typical (tpd < 4 ns)

• High-speed operation:

— 100 MHz@1.8V

— 200 MHz@2.5V/3.3V

• Industrial versions available

• Available packages include: SOIC, SSOP

Block Diagram

Pin Configuration

GND

Q10

VDD

GND

OE#

AVCMOS

VDD

Q10

OE#

GND

VDD

GND

VDD

3,10

15,22

VDD

GND

1,12,13

17,24

AVCMOS

24 pin SOIC/SSOP

GND

OUTPUT ^(AVCMOS)

Pin Description

Pin Number

1, 7, 8, 12, 13, 17, 20, 24

3,10,15,22

Pin Name

Pin Description

Power

G_ND

V_DD

OE#

Ground

Power Supply

Output Enable

Input

Power

LVTTL/LVCMOS

AVCMOS

2, 4, 9, 11, 14, 16, 18, 19, 21, 23 Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1 Output

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07347 Rev. *B

Revised December 26, 2002

12 3 4 5 6 7 8

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