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CY2CC810OXIT PDF预览

CY2CC810OXIT

更新时间: 2024-09-30 03:24:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟
页数 文件大小 规格书
9页 262K
描述
1:10 Clock Fanout Buffer

CY2CC810OXIT 数据手册

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CY2CC810  
1:10 Clock Fanout Buffer  
Features  
Description  
• Low-voltage operation  
The Cypress series of network circuits are produced using  
advanced 0.35-micron CMOS technology, achieving the  
industry’s fastest logic and buffers.  
• VDD range from 2.5V to 3.3V  
• 1:10 fanout  
The Cypress CY2CC810 fanout buffer features one input and  
ten outputs. Designed for data communications clock  
management applications, the large fanout from a single input  
reduces loading on the input clock.  
• Over voltage tolerant input hot swappable  
• Drives either a 50-Ohm or 75-Ohm transmission line  
• Low-input capacitance  
• 250 ps typical output-to-output skew  
• 19 ps typical DJ jitter  
AVCMOS-type outputs dynamically adjust for variable  
impedance matching and reduce noise overall.  
• Typical propagation delay < 3.5 ns  
• High-speed operation > 500 MHz  
• Industrial versions available  
• Available packages include: SOIC, SSOP  
.
Block Diagram  
Pin Configuration  
Q1  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VDD  
IN  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
Q8  
Q9  
Q10  
1
2
3
4
5
6
7
8
Q10  
Q9  
GND  
VDD  
Q1  
VDD  
Q2  
GND  
Q8  
VDD  
Q7  
GND  
Q3  
IN  
GND  
Q6  
INPUT  
VDD  
Q4  
9
10  
Q5  
GND  
20 pin SOIC/SSOP  
GND  
OUTPUT  
(AVCMOS)  
Pin Description  
Pin Number  
Pin Name  
IN  
Description  
1
Input  
Ground  
LVCMOS  
Power  
2, 6, 10, 13, 17  
GND  
4, 8, 15, 20  
VDD  
Power Supply  
Output  
Power  
3, 5, 7, 9, 11, 12, 14, 16, 18, 19  
Q1... Q10  
AVCMOS  
Cypress Semiconductor Corporation  
Document #: 38-07056 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised September 5, 2006  

CY2CC810OXIT 替代型号

型号 品牌 替代类型 描述 数据表
CY2CC810OXCT CYPRESS

完全替代

1:10 Clock Fanout Buffer
CY2CC810OXI CYPRESS

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1:10 Clock Fanout Buffer

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