CY2CC810SI

更新时间： 2024-09-29 22:28:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
7页	118K
描述
1:10 Clock Fanout Buffer

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数据手册

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CY2CC810SI 数据手册

COMLINK™ SERIES

CY2CC810

1:10 Clock Fanout Buffer

Features

Description

• Low-voltage operation

• V_DDrange from 2.5V to 3.3V

• 1:10 fanout

The Cypress series of network circuits are produced using

advanced 0.35-micron CMOS technology, achieving the

industries fastest logic and buffers.

The Cypress CY2CC810 fanout buffer features one input and

ten outputs. Designed for data communications clock

management applications, the large fanout from a single input

reduces loading on the input clock.

• Over voltage tolerant input hot swappable

• Drives either a 50-Ohm or 75-Ohm transmission line

• Low-input capacitance

• Low-output skew

• Low-propagation delay

AVCMOS-type outputs dynamically adjust for variable

impedance matching and eliminate the need for series

damping resistors; they also reduce noise overall.

• Typical (tpd < 4 ns)

• High-speed operation > 500 MHz

• Industrial versions available

• Available packages include: SOIC, SSOP

Block Diagram

Pin Configuration

VDD

Q10

GND

VDD

GND

VDD

GND

INPUT

VDD

Q10

GND

20 pin SOIC/SSOP

GND

OUTPUT

(AVCMOS)

Pin Description

Pin Number

Pin Name

Description

Input

Ground

LVCMOS

Power

2, 6, 10, 13, 17

GND

4, 8, 15, 20

V_DD

Power Supply

Output

Power

3, 5, 7, 9, 11, 12, 14, 16, 18, 19

Q1... Q10

AVCMOS

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07056 Rev. *C

Revised December 14, 2002

12 3 4 5 6 7

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