CY2CC910SCT

更新时间： 2024-11-24 22:28:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
8页	135K
描述
1:10 Clock Fanout Buffer

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数据手册

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CY2CC910SCT 数据手册

COMLINK™ SERIES

CY2CC910

1:10 Clock Fanout Buffer

— 650 MHz@2.5V/3.3V

Features

• Low-voltage operation

• Full-range support:

• Industrial versions available

• Available packages include: SOIC, SSOP

— 3.3V

— 2.5V

Description

The Cypress series of network circuits are produced using

advanced 0.35 micron CMOS technology, achieving the indus-

tries fastest logic and buffers.

— 1.8V

• Over voltage tolerant input hot swappable

• 1:10 fanout

• Drives either a 50-Ohm or 75-Ohm load

• Low-input capacitance

• Low-output skew

• Low-propagation delay

• Typical (tpd < 4 ns)

• High-speed operation:

— -200 MHz@1.8V

The Cypress CY2CC910 fanout buffer features one input and

ten outputs. Ideal for conversion from/to 3.3V/2.5V/1.8V

Designed for Data Communications clock management appli-

cations, the large fanout from a single input reduces loading

on the input clock.

Cypress employs unique AVCMOS type outputs VOI™

(Variable Output Impedance) that dynamically adjust for

variable impedance matching and eliminate the need for

series damping resistors and reduce noise overall.

Pin Configuration

Block Diagram

VDD

Q10

GND

VDD

GND

VDD

4,8

15,20

GND

VDD

INPUT

(AVCMOS)

2,6,10

GND

20 pin SOIC/SSOP

13,17

GND

OUTPUT

(AVCMOS)

Pin Description

Pin Number

Pin Name

Description

Input

2,6,10,13,17

GND

V_DD

Ground

4,8,15,20

Power Supply

Output

3,5,7,9,11,12,14,16,18,19

Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07348 Rev. *A

Revised October 3, 2002

12 3 4 5 6 7 8

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