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CY2CC910SIT PDF预览

CY2CC910SIT

更新时间: 2024-11-24 22:28:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 135K
描述
1:10 Clock Fanout Buffer

CY2CC910SIT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.300 INCH, MO-119, SOIC-20
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.76
其他特性:ALSO OPERATES WITH 2.5V AND 3.3V SUPPLY系列:2CC
输入调节:SCHMITT TRIGGERJESD-30 代码:R-PDSO-G20
JESD-609代码:e0长度:12.827 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER最大I(ol):0.012 A
功能数量:1反相输出次数:
端子数量:20实输出次数:10
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.8/3.3 VProp。Delay @ Nom-Sup:3.5 ns
传播延迟(tpd):3.5 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.2 ns座面最大高度:2.667 mm
子类别:Clock Drivers最大供电电压 (Vsup):1.89 V
最小供电电压 (Vsup):1.71 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

CY2CC910SIT 数据手册

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COMLINK™ SERIES  
CY2CC910  
1:10 Clock Fanout Buffer  
650 MHz@2.5V/3.3V  
Features  
Low-voltage operation  
Full-range support:  
Industrial versions available  
Available packages include: SOIC, SSOP  
3.3V  
2.5V  
Description  
The Cypress series of network circuits are produced using  
advanced 0.35 micron CMOS technology, achieving the indus-  
tries fastest logic and buffers.  
1.8V  
Over voltage tolerant input hot swappable  
1:10 fanout  
Drives either a 50-Ohm or 75-Ohm load  
Low-input capacitance  
Low-output skew  
Low-propagation delay  
Typical (tpd < 4 ns)  
High-speed operation:  
-200 MHz@1.8V  
The Cypress CY2CC910 fanout buffer features one input and  
ten outputs. Ideal for conversion from/to 3.3V/2.5V/1.8V  
Designed for Data Communications clock management appli-  
cations, the large fanout from a single input reduces loading  
on the input clock.  
Cypress employs unique AVCMOS type outputs VOI™  
(Variable Output Impedance) that dynamically adjust for  
variable impedance matching and eliminate the need for  
series damping resistors and reduce noise overall.  
Pin Configuration  
Block Diagram  
3
5
Q1  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VDD  
IN  
1
2
3
4
5
6
7
8
Q10  
Q9  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
Q8  
Q9  
Q10  
GND  
Q1  
VDD  
Q2  
7
GND  
Q8  
VDD  
9
VDD  
Q7  
4,8  
15,20  
GND  
Q3  
11  
GND  
Q6  
VDD  
Q4  
IN  
1
9
10  
12  
14  
16  
18  
19  
Q5  
INPUT  
(AVCMOS)  
2,6,10  
GND  
20 pin SOIC/SSOP  
13,17  
GND  
OUTPUT  
(AVCMOS)  
Pin Description  
Pin Number  
Pin Name  
Description  
1
IN  
Input  
2,6,10,13,17  
GND  
VDD  
Ground  
4,8,15,20  
Power Supply  
Output  
3,5,7,9,11,12,14,16,18,19  
Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-07348 Rev. *A  
Revised October 3, 2002  

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