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CY2DL1504

更新时间: 2024-10-01 09:41:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟
页数 文件大小 规格书
14页 302K
描述
1:4 Differential LVDS Fanout Buffer with Selectable Clock Input

CY2DL1504 数据手册

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CY2DL1504  
1:4 Differential LVDS Fanout Buffer  
with Selectable Clock Input  
Features  
Functional Description  
Select between low-voltage positive emitter-coupled logic  
(LVPECL) or low-voltage differential signal (LVDS) input pairs  
to distribute to four LVDS output pairs  
The CY2DL1504 is an ultra-low noise, low-skew,  
low-propagation delay 1:4 differential LVDS fanout buffer  
targeted to meet the requirements of high-speed clock  
distribution applications. The CY2DL1504 can select between  
LVPECL or LVDS input clock pairs using the IN_SEL pin. The  
synchronous clock enable function ensures glitch-free output  
transitions during enable and disable periods. The output enable  
function allows the outputs to be asynchronously driven to a  
high-impedance state. The device has a fully differential internal  
architecture that is optimized to achieve low-additive jitter and  
low-skew at operating frequencies of up to 1.5 GHz.  
30-ps maximum output-to-output skew  
480-ps maximum propagation delay  
0.11-ps maximum additive RMS phase jitter at 156.25 MHz  
(12-kHz to 20-MHz offset)  
Up to 1.5-GHz operation  
Output enable and synchronous clock enable functions  
20-pin thin shrunk small outline package (TSSOP)  
2.5-V or 3.3-V operating voltage[1]  
Commercial and industrial operating temperature range  
Logic Block Diagram  
VDD  
VSS  
Q0  
Q0#  
IN0  
IN0#  
Q1  
Q1#  
IN1  
IN1#  
Q2  
Q2#  
IN_SEL  
Q3  
Q3#  
RP  
VDD  
Q
RP  
D
CLK_EN  
VDD  
RP  
OE  
Note  
1. Input AC-coupling capacitors are required for voltage-translation applications.  
Cypress Semiconductor Corporation  
Document Number: 001-56312 Rev. *F  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 29, 2011  
[+] Feedback  

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