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CY2DL814ZIT PDF预览

CY2DL814ZIT

更新时间: 2024-09-30 22:17:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 114K
描述
1:4 Clock Fanout Buffer

CY2DL814ZIT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:4.40 MM, MO-153, TSSOP-16
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.78
Is Samacsys:N系列:2DL
输入调节:DIFFERENTIALJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:5 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:16实输出次数:4
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):235
电源:3.3 VProp。Delay @ Nom-Sup:5 ns
传播延迟(tpd):5 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.2 ns座面最大高度:1.1 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

CY2DL814ZIT 数据手册

 浏览型号CY2DL814ZIT的Datasheet PDF文件第2页浏览型号CY2DL814ZIT的Datasheet PDF文件第3页浏览型号CY2DL814ZIT的Datasheet PDF文件第4页浏览型号CY2DL814ZIT的Datasheet PDF文件第5页浏览型号CY2DL814ZIT的Datasheet PDF文件第6页浏览型号CY2DL814ZIT的Datasheet PDF文件第7页 
ComLink™ Series  
CY2DL814  
1:4 Clock Fanout Buffer  
Features  
Description  
Low-voltage operation  
VDD = 3.3V  
1:4 Fanout  
The Cypress CY2 series of network circuits is produced using  
advanced 0.35-micron CMOS technology, achieving the  
industrys fastest logic.  
The Cypress CY2DL814 fanout buffer features a single  
LVDS-, LVPECL-, or LVTTL-compatible input and four LVDS  
output pairs.  
Single-input configurable for  
LVDS, LVPECL, or LVTTL  
Four differential pairs of LVDS outputs  
Drives 50- or 100-ohm load (selectable)  
Low input capacitance  
Designed for data-communication clock management applica-  
tions, the fanout from a single input reduces loading on the  
input clock.  
Low output skew  
Does not exceed Bellcore 802.3 standards  
The CY2DL814 is ideal for both level translations from single  
ended to LVDS and/or for the distribution of LVDS-based clock  
signals. The Cypress CY2DL814 has configurable input and  
output functions. The input can be selectable for  
LVPECL/LVTTL or LVDS signals while the output drivers  
support standard and high drive LVDS. Drive either a 50-ohm  
or 100-ohm line with a single part number/device.  
Operation at  
350 MHz 700 Mbps  
Low propagation delay Typical (tpd < 4 ns)  
Industrial versions available  
Packages available include TSSOP/SOIC  
Block Diagram  
Pin Configuration  
EN1  
EN2  
EN1  
16  
15  
14  
13  
12  
11  
Q1A  
Q1B  
1
2
3
4
5
6
7
8
CONFIG  
CNTRL  
VDD  
Q1A  
Q1B  
Q2A  
Q2B  
Q3A  
Q3B  
Q4A  
Q4B  
GND  
IN+  
Q2A  
Q2B  
IN+  
IN-  
IN-  
10  
9
EN2  
LVDS /  
LVPECL /  
LVTTL  
Q3A  
Q3B  
16-pin TSSOP/SOIC  
CONFIG  
Q4A  
Q4B  
CNTRL  
OUTPUT  
LVDS  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-07057 Rev. *A  
Revised December 14, 2002  

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1:2 CML / LVPECL Input to CML Output Fanout Buffer