CY2DL818

更新时间： 2024-10-01 04:13:19

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
8页	103K
描述
1:8 Clock Fanout Buffer

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CY2DL818 数据手册

CY2DL818

1:8 Clock Fanout Buffer

Features

Description

• Low voltage operation

• V_DD= 3.3V

• 1:8 fanout

This Cypress series of network circuits is produced using

advanced 0.35-micron CMOS technology, achieving the

industry’s fastest logic.

The Cypress CY2DL818 fanout buffer features a single LVDS

or a single-ended LVTTL-compatible input and eight LVDS

output pairs.

• Single-input-configurable for LVDS, LVPECL, or LVTTL

• 8 pair of LVDS Outputs

• Drives either a 50-ohm or 100-ohm load (selectable)

• Low input capacitance

• Low output skew

• Low propagation delay

Designed for data communications clock management appli-

cations, the large fanout from a single input reduces loading

on the input clock. The Cypress CY2DL818 is ideal for both

level translations from single-ended to LVDS and/or for the

distribution of LVDS-based clock signals.

• Typical (tpd < 4 ns)

• Packages available include: TSSOP

• Does not exceed Bellcore 802.3 standards

• Operation at => 350 MHz – 700 Mbps

The Cypress CY2DL818 has configurable input and output

functions. The input can be selectable for LVCMOS/LVTTL,

LVPECL, or LVDS signals, while the output drivers support

standard and high-drive LVDS. Drive either a 50-ohm or

100-ohm line with a single part number/device.

Pin Configuration

Block Diagram

Q1A

Q1B

GND

VDD

GND

Q1A

Q1B

Q2A

Q2B

Q3A

Q3B

Q4A

Q4B

Q2A

Q2B

InConfig

CNTRL

Q3A

INPUT

(LVPECL / LVDS / LVTTL)

Q3B

VDD

GND

VDD

Q5A

INPUT A

INPUT B

Q4A

INPUT A

INPUT B

Q4B

Q5B

Q6A

Q6B

Q7A

Q7B

Q8A

Q8B

GND

GND 12

VDD

Q5A

Q5B

InConfig

VDD

Q6A

Q6B

GND

Q7A

Q7B

38 pin TSSOP

Q8A

Q8B

CNTRL

OUTPUT

(LVDS)

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07058 Rev. *B

Revised December 15, 2002

12 3 4 5 6 7 8

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