CY2DP3110AI

更新时间： 2024-11-20 04:13:19

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
9页	279K
描述
1 of 2:10 Differential Clock/Data Fanout Buffer

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CY2DP3110AI 数据手册

FastEdge™ Series

CY2DP3110

1 of 2:10 Differential Clock/Data Fanout Buffer

Features

• Ten ECL/PECL differential outputs

• One ECL/PECL differential or single-ended inputs

(CLKA)

• One HSTL differential or single-ended inputs (CLKB)

• Hot-swappable/-insertable

• 50 ps output-to-output skew

• 150 ps device-to-device skew

• 400 ps propagation delay (typical)

• 1.2 ps RMS period jitter (max.)

• 1.5 GHz Operation (2.7 GHz maximum toggle

frequency)

• PECL and HSTL mode supply range: V_CC= 2.5V± 5% to

3.3V±5% with V_EE= 0V

• ECL mode supply range: V_{E E}= –2.5V± 5% to –3.3V±5%

with V_CC= 0V

• Industrial temperature range: –40°C to 85°C

• 32-pin TQFP package

• Temperature compensation like 100K ECL

• Pin-compatible with MC100ES6111

Functional Description

The CY2DP3110 is a low-skew, low propagation delay 2-to-10

differential fanout buffer targeted to meet the requirements of

high-performance clock and data distribution applications. The

device is implemented on SiGe technology and has a fully

differential internal architecture that is optimized to achieve

low signal skews at operating frequencies of up to 1.5 GHz.

The device features two differential input paths that are multi-

plexed internally. This mux is controlled by the CLK_SEL pin.

The CY2DP3110 may function not only as a differential clock

buffer but also as a signal-level translator and fanout on HSTL

single-ended signal to 10 ECL/PECL differential loads. An ex-

ternal bias pin, VBB, is provided for this purpose. In such an

application, the VBB pin should be connected to either one of

the CLKA# or CLKB# inputs and bypassed to ground via a

0.01-µF capacitor. Traditionally, in ECL, it is used to provide

the reference level to a receiving single-ended input that might

have a different self-bias point.

Since the CY2DP3110 introduces negligible jitter to the timing

budget, it is the ideal choice for distributing high frequency,

high precision clocks across back-planes and boards in com-

munication systems. Furthermore, advanced circuit design

schemes, such as internal temperature compensation, ensure

that the CY2DP3110 delivers consistent performance over

various platforms

Block Diagram

Pin Configuration

V_BB

Q0#

Q1#

VCC

CLK_SEL

CLKA

CLKA#

VBB

CLKB

Q3#

Q4#

Q5#

Q6#

CLKA

Q2#

CLKA#

VEE

CY2DP3110

Q3#

VCC

CLKB

CLKB#

VEE

CLKB#

Q4#

VEE

CLK_SEL

Q5#

VEE

Q6#

VBB

Q7#

Q8#

Q9#

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07469 Rev.*G

Revised July 28, 2004

12 3 4 5 6 7...9

中文翻译

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CY2DP3110AI 替代型号

型号	品牌	替代类型	描述	数据表
CY2305CSXA-1H	CYPRESS	类似代替	3.3V Zero Delay Clock Buffer
CY2309NZSXC-1H	CYPRESS	功能相似	Nine-Output 3.3V Buffer
CY2305SXC-1	CYPRESS	功能相似	Low-Cost 3.3V Zero Delay Buffer

与CY2DP3110AI相关器件

型号	品牌	获取价格	描述	数据表
CY2DP3110AIT	CYPRESS	获取价格	1 of 2:10 Differential Clock/Data Fanout Buffer
CY2DP3110AXI	CYPRESS	获取价格	Low Skew Clock Driver, 2DP Series, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7
CY2DP3110AXIT	CYPRESS	获取价格	Low Skew Clock Driver, 2DP Series, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7
CY2DP3120	CYPRESS	获取价格	1:20 Differential Clock/Data Fanout Buffer
CY2DP3120AI	CYPRESS	获取价格	1:20 Differential Clock/Data Fanout Buffer
CY2DP3120AIT	CYPRESS	获取价格	1:20 Differential Clock/Data Fanout Buffer
CY2DP3120AXI	CYPRESS	获取价格	1:20 Differential Clock/Data Fanout Buffer
CY2DP3120AXIT	CYPRESS	获取价格	1:20 Differential Clock/Data Fanout Buffer
CY2DP314	CYPRESS	获取价格	1 of 2:4 Differential Clock/Data Fanout Buffer
CY2DP314_05	CYPRESS	获取价格	1:4 Differential Clock/Data Fanout Buffer

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