CY2DP1502

更新时间： 2024-10-01 12:20:19

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
13页	482K
描述
1:2 LVPECL Fanout Buffer 20-ps maximum output-to-output skew

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数据手册

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CY2DP1502 数据手册

CY2DP1502

1:2 LVPECL Fanout Buffer

Features

Functional Description

■ One low-voltage positive emitter-coupled logic (LVPECL) input

pair distributed to two LVPECL output pairs

The CY2DP1502 is an ultra-low noise, low-skew,

low-propagation delay 1:2 LVPECL fanout buffer targeted to

meet the requirements of high-speed clock distribution

applications. The device has a fully differential internal

architecture that is optimized to achieve low additive jitter and

low skew at operating frequencies of up to 1.5 GHz.

■ 20-ps maximum output-to-output skew

■ 480-ps maximum propagation delay

■ 0.15-ps maximum additive RMS phase jitter at 156.25 MHz

(12-kHz to 20-MHz offset)

■ Up to 1.5-GHz operation

■ 8-pin small outline integrated circuit (SOIC) or 8-pin thin shrunk

small outline package (TSSOP) package

■ 2.5-V or 3.3-V operating voltage^[1]

■ Commercial and industrial operating temperature range

Logic Block Diagram

V_DD

V_SS

Q0#

Q1#

IN#

Note

1. Input AC-coupling capacitors are required for voltage-translation applications.

Cypress Semiconductor Corporation

Document Number: 001-56308 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 19, 2011

12 3 4 5 6 7...13

中文翻译

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CY2DP1502SXC	CYPRESS	获取价格	1:2 LVPECL Fanout Buffer 20-ps maximum output-to-output skew
CY2DP1502SXCT	CYPRESS	获取价格	1:2 LVPECL Fanout Buffer 20-ps maximum output-to-output skew
CY2DP1502SXI	CYPRESS	获取价格	1:2 LVPECL Fanout Buffer 20-ps maximum output-to-output skew
CY2DP1502SXIT	CYPRESS	获取价格	1:2 LVPECL Fanout Buffer 20-ps maximum output-to-output skew
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CY2DP1502ZXCT	CYPRESS	获取价格	1:2 LVPECL Fanout Buffer 20-ps maximum output-to-output skew
CY2DP1502ZXI	CYPRESS	获取价格	1:2 LVPECL Fanout Buffer 20-ps maximum output-to-output skew
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