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CY2DP3110AXIT

更新时间： 2024-10-01 21:05:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 驱动逻辑集成电路
页数 文件大小 规格书
10页 304K
描述
Low Skew Clock Driver, 2DP Series, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, TQFP-32

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CY2DP3110AXIT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP,针数：32
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.8其他特性：ECL MODE: VCC = 0V WITH VEE = -2.375V TO -3.465V; ALSO OPERATES AT 3.3V SUPPLY
系列：2DP输入调节：DIFFERENTIAL MUX
JESD-30 代码：S-PQFP-G32JESD-609代码：e3
长度：7 mm逻辑集成电路类型：LOW SKEW CLOCK DRIVER
湿度敏感等级：3功能数量：1
反相输出次数：端子数量：32
实输出次数：10最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE峰值回流温度（摄氏度）：260
传播延迟（tpd）：0.75 ns认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.05 ns座面最大高度：1.6 mm
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：7 mm最小 fmax：1500 MHz
Base Number Matches：1

CY2DP3110AXIT 数据手册

 浏览型号CY2DP3110AXIT的Datasheet PDF文件第2页浏览型号CY2DP3110AXIT的Datasheet PDF文件第3页浏览型号CY2DP3110AXIT的Datasheet PDF文件第4页浏览型号CY2DP3110AXIT的Datasheet PDF文件第5页浏览型号CY2DP3110AXIT的Datasheet PDF文件第6页浏览型号CY2DP3110AXIT的Datasheet PDF文件第7页 
FastEdge™ Series  
CY2DP3110  
1 of 2:10 Differential Clock/Data Fanout Buffer  
Features  
• Ten ECL/PECL differential outputs  
• One ECL/PECL differential or single-ended inputs  
(CLKA)  
• One HSTL differential or single-ended inputs (CLKB)  
• Hot-swappable/-insertable  
• 29 ps typical output-to-output skew  
• 95 ps typical part-to-part skew  
• 400 ps typical propagation delay  
• 0.1 ps typical RMS phase jitter  
• 1.5 GHz Operation (2.7 GHz maximum toggle  
frequency)  
• PECL and HSTL mode supply range: VCC = 2.5V± 5% to  
3.3V±5% with VEE = 0V  
• ECL mode supply range: VE E = –2.5V± 5% to –3.3V±5%  
with VCC = 0V  
• Industrial temperature range: –40°C to 85°C  
• 32-pin TQFP package  
• Temperature compensation like 100K ECL  
• Pin-compatible with MC100ES6111  
Functional Description  
The CY2DP3110 is a low-skew, low propagation delay 2-to-10  
differential fanout buffer targeted to meet the requirements of  
high-performance clock and data distribution applications. The  
device is implemented on SiGe technology and has a fully  
differential internal architecture that is optimized to achieve  
low signal skews at operating frequencies of up to 1.5 GHz.  
The device features two differential input paths that are multi-  
plexed internally. This mux is controlled by the CLK_SEL pin.  
The CY2DP3110 may function not only as a differential clock  
buffer but also as a signal-level translator and fanout on HSTL  
single-ended signal to 10 ECL/PECL differential loads. An ex-  
ternal bias pin, VBB, is provided for this purpose. In such an  
application, the VBB pin should be connected to either one of  
the CLKA# or CLKB# inputs and bypassed to ground via a  
0.01-µF capacitor. Traditionally, in ECL, it is used to provide  
the reference level to a receiving single-ended input that might  
have a different self-bias point.  
Since the CY2DP3110 introduces negligible jitter to the timing  
budget, it is the ideal choice for distributing high frequency,  
high precision clocks across back-planes and boards in com-  
munication systems. Furthermore, advanced circuit design  
schemes, such as internal temperature compensation, ensure  
that the CY2DP3110 delivers consistent performance over  
various platforms  
Block Diagram  
Pin Configuration  
VBB  
Q0  
Q0#  
Q1  
Q1#  
VCC  
1
2
3
4
5
6
7
8
VCC  
CLK_SEL  
CLKA  
CLKA#  
VBB  
CLKB  
Q3  
Q3#  
Q4  
Q4#  
Q5  
Q5#  
Q6  
Q6#  
24  
23  
22  
21  
20  
19  
18  
17  
Q2  
CLKA  
Q2#  
CLKA#  
Q3  
VEE  
CY2DP3110  
Q3#  
VCC  
Q4  
CLKB  
CLKB#  
VEE  
CLKB#  
Q4#  
Q5  
VEE  
CLK_SEL  
Q5#  
Q6  
VEE  
Q6#  
Q7  
VBB  
Q7#  
Q8  
Q8#  
Q9  
Q9#  
Cypress Semiconductor Corporation  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Document #: 38-07469 Rev. *I  
Revised August 18, 2005  
1234567...10

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