Datasheet > CY2DP818-2

CY2DP818-2

更新时间： 2024-10-01 04:13:19

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
8页	133K
描述
1:8 Clock Fanout Buffer

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中文翻译

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数据手册

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CY2DP818-2 数据手册

PRELIMINARY

CY2DP818-2

1:8 Clock Fanout Buffer

Features

Description

• Low-voltage operation V_DD= 3.3V

• 1:8 fanout

This Cypress series of network circuits is produced using

advanced 0.35-micron CMOS technology, achieving the

industry’s fastest logic.

• Single-input-configurable for LVDS, LVPECL, or LVTTL

• 8 pairs of LVPECL outputs with enable/disable

• Drives a 50-ohm load

The Cypress CY2DP818-2 fanout buffer features a single

LVDS or a single-ended LVTTL-compatible input and eight

LVPECL output pairs.

Designed for data-communications clock-management appli-

cations, the large fanout from a single input reduces loading

on the input clock.

• Low input capacitance

• Low output skew

• Low propagation delay Typical (tpd < 4 ns)

• Industrial versions available

The CY2DP818-2 is ideal for both level translations from

single-ended to LVPECL and/or for the distribution of

LVPECL-based clock signals.

• Package available include: TSSOP

• Does not exceed Bellcore 802.3 standards

• Operation up to 350 MHz/700 Mbps

The Cypress CY2DP818-2 has configurable input functions.

The input is user-configurable via the Inconfig pin for single

ended or differential input.

Pin Configuration

Block Diagram

EN1

Q1A

Q1B

GND

Q1A

Q1B

Q2A

Q2B

Q3A

Q3B

Q4A

Q4B

GND

VDD

EN1

EN2

Q2A

Q2B

EN2

EN3

EN4

EN3

Q3A

InConfig

INPUT

Q3B

VDD

GND

(LVPECL / LVDS / LVTTL)

EN4

Q4A

VDD

Q5A

INPUT A

INPUT B

GND

INPUT A

INPUT B

Q4B

Q5B

Q6A

Q6B

Q7A

Q7B

Q8A

EN5

Q5A

VDD

EN5

InConfig

Q5B

EN6

Q6A

Q6B

EN7

VDD

GND

Q8B

Q7A

Q7B

GND

EN7

38-pin TSSOP

Q8A

Q8B

OUTPUT

(LVPECL)

Cypress Semiconductor Corporation

Document #: 38-07588 Rev. **

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised November 5, 2003

12 3 4 5 6 7 8

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