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CY2DP818ZI-2T

更新时间: 2024-11-20 03:12:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟
页数 文件大小 规格书
8页 133K
描述
1:8 Clock Fanout Buffer

CY2DP818ZI-2T 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:4.40 MM, TSSOP-38
针数:38Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.72
系列:2DP输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G38JESD-609代码:e0
长度:9.7 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:38
实输出次数:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP38,.25,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
Prop。Delay @ Nom-Sup:5 ns传播延迟(tpd):5 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.2 ns
座面最大高度:1.1 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

CY2DP818ZI-2T 数据手册

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PRELIMINARY  
CY2DP818-2  
1:8 Clock Fanout Buffer  
Features  
Description  
• Low-voltage operation VDD = 3.3V  
• 1:8 fanout  
This Cypress series of network circuits is produced using  
advanced 0.35-micron CMOS technology, achieving the  
industry’s fastest logic.  
• Single-input-configurable for LVDS, LVPECL, or LVTTL  
• 8 pairs of LVPECL outputs with enable/disable  
• Drives a 50-ohm load  
The Cypress CY2DP818-2 fanout buffer features a single  
LVDS or a single-ended LVTTL-compatible input and eight  
LVPECL output pairs.  
Designed for data-communications clock-management appli-  
cations, the large fanout from a single input reduces loading  
on the input clock.  
• Low input capacitance  
• Low output skew  
• Low propagation delay Typical (tpd < 4 ns)  
• Industrial versions available  
The CY2DP818-2 is ideal for both level translations from  
single-ended to LVPECL and/or for the distribution of  
LVPECL-based clock signals.  
• Package available include: TSSOP  
• Does not exceed Bellcore 802.3 standards  
• Operation up to 350 MHz/700 Mbps  
The Cypress CY2DP818-2 has configurable input functions.  
The input is user-configurable via the Inconfig pin for single  
ended or differential input.  
Pin Configuration  
Block Diagram  
EN1  
Q1A  
Q1B  
GND  
Q1A  
Q1B  
Q2A  
Q2B  
Q3A  
Q3B  
Q4A  
Q4B  
GND  
VDD  
EN1  
1
2
3
4
5
6
7
8
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
EN2  
Q2A  
Q2B  
EN2  
EN3  
EN4  
EN3  
Q3A  
InConfig  
INPUT  
Q3B  
VDD  
GND  
(LVPECL / LVDS / LVTTL)  
EN4  
9
Q4A  
VDD  
Q5A  
INPUT A  
INPUT B  
GND  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
INPUT A  
INPUT B  
Q4B  
Q5B  
Q6A  
Q6B  
Q7A  
Q7B  
Q8A  
EN5  
Q5A  
VDD  
EN5  
InConfig  
Q5B  
EN6  
EN6  
Q6A  
Q6B  
EN7  
VDD  
GND  
Q8B  
Q7A  
Q7B  
GND  
GND  
EN7  
38-pin TSSOP  
Q8A  
Q8B  
OUTPUT  
(LVPECL)  
Cypress Semiconductor Corporation  
Document #: 38-07588 Rev. **  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised November 5, 2003  

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