Datasheet > CY2DP818-2_08

CY2DP818-2_08

更新时间： 2024-11-20 06:51:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
9页	409K
描述
1:8 Clock Fanout Buffer

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数据手册

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CY2DP818-2_08 数据手册

PRELIMINARY

CY2DP818-2

1:8 Clock Fanout Buffer

Features

Description

■ Low voltage operation V_DD= 3.3V

■ 1:8 fanout

This Cypress series of network circuits is produced using

advanced 0.35 micron CMOS technology, achieving the

industry’s fastest logic.

■ Single-input configurable for LVDS, LVPECL, or LVTTL

■ 8 pairs of LVPECL outputs with enable and disable

■ Drives a 50 ohm load

The Cypress CY2DP818-2 fanout buffer features a single

LVDS or a single-ended LVTTL compatible input and eight

LVPECL output pairs.

Designed for data communications clock management appli-

cations, the large fanout from a single input reduces loading

on the input clock.

■ Low input capacitance

■ Low output skew

The CY2DP818-2 is ideal for both level translations from

single-ended to LVPECL and for the distribution of LVPECL

based clock signals.

■ Low propagation delay typical (tpd < 4 ns)

■ Industrial versions available

The Cypress CY2DP818-2 has configurable input functions.

The input is user configurable through the Inconfig pin for

single ended or differential input.

■ Package available include: TSSOP

■ Does not exceed Bellcore 802.3 standards

■ Operation up to 350 MHz and 700 Mbps

Logic Block Diagram

EN1

Q1A

Q1B

EN2

EN3

Q2A

Q2B

Q3A

Q3B

INPUT

(LVPECL / LVDS / LVTTL)

EN4

EN5

EN6

Q4A

Q4B

INPUT A

INPUT B

Q5A

Q5B

InConfig

Q6A

Q6B

Q7A

Q7B

EN7

Q8A

Q8B

OUTPUT

(LVPECL)

Cypress Semiconductor Corporation

Document #: 38-07588 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised October 22, 2008

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