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CY2DP818ZXC-2T PDF预览

CY2DP818ZXC-2T

更新时间: 2024-11-20 06:51:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
9页 409K
描述
1:8 Clock Fanout Buffer

CY2DP818ZXC-2T 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP38,.25,20
针数:38Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.66
系列:2DP输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G38长度:9.7 mm
逻辑集成电路类型:CLOCK DRIVER功能数量:1
反相输出次数:端子数量:38
实输出次数:16最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP38,.25,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源:3.3 VProp。Delay @ Nom-Sup:5 ns
传播延迟(tpd):5 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.2 ns座面最大高度:1.1 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
宽度:4.4 mmBase Number Matches:1

CY2DP818ZXC-2T 数据手册

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PRELIMINARY  
CY2DP818-2  
1:8 Clock Fanout Buffer  
Features  
Description  
Low voltage operation VDD = 3.3V  
1:8 fanout  
This Cypress series of network circuits is produced using  
advanced 0.35 micron CMOS technology, achieving the  
industry’s fastest logic.  
Single-input configurable for LVDS, LVPECL, or LVTTL  
8 pairs of LVPECL outputs with enable and disable  
Drives a 50 ohm load  
The Cypress CY2DP818-2 fanout buffer features a single  
LVDS or a single-ended LVTTL compatible input and eight  
LVPECL output pairs.  
Designed for data communications clock management appli-  
cations, the large fanout from a single input reduces loading  
on the input clock.  
Low input capacitance  
Low output skew  
The CY2DP818-2 is ideal for both level translations from  
single-ended to LVPECL and for the distribution of LVPECL  
based clock signals.  
Low propagation delay typical (tpd < 4 ns)  
Industrial versions available  
The Cypress CY2DP818-2 has configurable input functions.  
The input is user configurable through the Inconfig pin for  
single ended or differential input.  
Package available include: TSSOP  
Does not exceed Bellcore 802.3 standards  
Operation up to 350 MHz and 700 Mbps  
Logic Block Diagram  
EN1  
Q1A  
Q1B  
EN2  
EN3  
Q2A  
Q2B  
Q3A  
Q3B  
INPUT  
(LVPECL / LVDS / LVTTL)  
EN4  
EN5  
EN6  
Q4A  
Q4B  
INPUT A  
INPUT B  
Q5A  
Q5B  
InConfig  
Q6A  
Q6B  
Q7A  
Q7B  
EN7  
Q8A  
Q8B  
OUTPUT  
(LVPECL)  
Cypress Semiconductor Corporation  
Document #: 38-07588 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised October 22, 2008  
[+] Feedback  

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