Datasheet > CY2DP814_08

CY2DP814_08

更新时间： 2024-11-20 06:51:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
9页	428K
描述
1:4 Clock Fanout Buffer

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CY2DP814_08 数据手册

CY2DP814

1:4 Clock Fanout Buffer

Features

Description

■ Low-voltage operation

The Cypress CY2 series of network circuits are produced

using advanced 0.35-micron CMOS technology, achieving the

industry’s fastest logic.

■ V_DD= 3.3V

■ 1:4 fanout

The Cypress CY2DP814 fanout buffer features a single LVDS-

or a single LVPECL-compatible input and four LVPECL output

pairs.

■ Single input configurable for LVDS, LVPECL, or LVTTL

■ Four differential pairs of LVPECL outputs

■ Drives 50-ohm load

Designed for data communications clock management appli-

cations, the fanout from a single input reduces loading on the

input clock.

■ Low input capacitance

The CY2DP814 is ideal for both level translations from

single-ended to LVPECL, and/or for the distribution of

LVDS-based clock signals. The Cypress CY2DP814 has

configurable input between logic families. The input can be

selectable for an LVPECL, LVTTL or LVDS signal, while the

output drivers support LVPECL capable of driving 50-ohm

lines.

■ Less than 4 ns typical propagation delay

■ 85 ps typical output-to-output skew

■ Industrial versions available

■ Available in TSSOP package

Logic Block Diagram

EN1 1

EN2 8

16 Q1A

15 Q1B

14 Q2A

13 Q2B

IN+ 6

IN-

LVDS /

LVPECL /

LVTTL

12 Q3A

11 Q3B

CONFIG 2

10 Q4A

9 Q4B

OUTPUT

LVPECL

Cypress Semiconductor Corporation

Document #: 38-07060 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised October 22, 2008

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