CY2DP818

更新时间： 2024-09-30 22:40:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
8页	95K
描述
1:8 Clock Fanout Buffer

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中文翻译

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数据手册

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CY2DP818 数据手册

ComLink™ Series

CY2DP818

1:8 Clock Fanout Buffer

Features

Description

• Low-voltage operation V_DD= 3.3V

• 1:8 fanout

• Single-input-configurable for LVDS, LVPECL, or LVTTL

• 8 pair of LVPECL outputs

• Drives a 50-ohm load

• Low input capacitance

This Cypress series of network circuits are produced using

advanced 0.35-micron CMOS technology, achieving the

industry’s fastest logic.

The Cypress CY2DP818 fanout buffer features a single LVDS

or a single-ended LVTTL-compatible input and eight LVPECL

output pairs.

Designed for data-communications clock-management appli-

cations, the large fanout from a single input reduces loading

on the input clock.

• Low output skew

• Low propagation delay Typical (tpd < 4 ns)

• Industrial versions available

• Package available include: TSSOP

• Does not exceed Bellcore 802.3 standards

• Operation at 350 MHz–700 Mbps

The CY2DP818 is ideal for both level translations from

single-ended to LVPECL and/or for the distribution of

LVPECL-based clock signals.

The Cypress CY2DP818 has configurable input functions. The

input is user configurable via the Inconfig pin for single ended

or differential input.

Pin Configuration

Block Diagram

Q1A

Q1B

GND

VDD

GND

Q1A

Q1B

Q2A

Q2B

Q3A

Q3B

Q4A

Q4B

Q2A

Q2B

VDD

Q3A

INPUT

(LVPECL / LVDS / LVTTL)

InConfig

VDD

Q3B

GND

Q4A

INPUT A

INPUT B

VDD

Q5A

INPUT A

Q4B

INPUT B

GND

Q5B

Q6A

Q6B

Q7A

Q7B

Q8A

Q8B

GND

Q5A

VDD

InConfig

Q5B

VDD

Q6A

Q6B

VDD

GND

Q7A

Q7B

Q8A

Q8B

38-pin TSSOP

OUTPUT

(LVPECL)

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07061 Rev. *A

Revised July 9, 2002

12 3 4 5 6 7 8

中文翻译

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