Datasheet > CY2DP314_05

CY2DP314_05

更新时间： 2024-11-20 04:13:19

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
10页	229K
描述
1:4 Differential Clock/Data Fanout Buffer

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CY2DP314_05 数据手册

CY2DP314

1:4 Differential Clock/Data Fanout Buffer

Features

• Four ECL/PECL differential outputs

• One ECL/PECL differential or single-ended inputs

(CLKA)

• One HSTL differential or single-ended inputs (CLKB)

• Hot-swappable/-insertable

Functional Description

The CY2DP314 is a low-skew, low propagation delay 2-to-4

differential fanout buffer targeted to meet the requirements of

high-performance clock and data distribution applications. The

device is implemented on SiGe technology and has a fully

differential internal architecture that is optimized to achieve

low signal skews at operating frequencies of up to 1.5 GHz (full

swing).

The device features two differential input paths that are multi-

plexed internally. This mux is controlled by the CLK_SEL pin.

The CY2DP314 may function not only as a differential clock

buffer but also as a signal-level translator and fanout on HSTL

or LVCMOS /LVTTL single-ended signal to four ECL/PECL

differential loads.

Since the CY2DP314 introduces negligible jitter to the timing

budget, it is the ideal choice for distributing high frequency,

high precision clocks across back-planes and boards in

communication systems. Furthermore, advanced circuit

design schemes, such as internal temperature compensation,

ensure that the CY2DP314 delivers consistent performance

over various platforms.

• 29 ps typical output-to-output skew

• 95 ps typical part-to-part skew

• 400 ps typical propagation delay

• 0.16 ps typical RMS phase jitter

• 7 ps typical peak period jitter

• 1.5-GHz operation (2.7-GHz maximum toggle

frequency)

• PECL and HSTL mode supply range: V_CC= 2.5V± 5% to

3.3V±5% with V_EE= 0V

• ECL mode supply range: V_{E E}= –2.5V± 5% to –3.3V±5%

with V_CC= 0V

• Industrial temperature range: –40°C to 85°C

• 20-pin SSOP package

• Temperature compensation like 100K ECL

Block Diagram

Pin Configuration

VCC

Q0#

VCC

Q0#

Q1#

Q2#

Q3#

VCC

CLK_SEL

CLKA

CLKA#

CLKB

CLKB#

VEE

CLKA

CLKA#

Q1#

VEE

VCC

Q2#

CLKB

CLKB#

Q3#

VEE

CLK_SEL

VCC

20-pin SSOP

VEE

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Document #: 38-07550 Rev.*G

Revised August 22, 2005

12 3 4 5 6 7...10

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与CY2DP314_05相关器件

型号	品牌	获取价格	描述	数据表
CY2DP314OI	CYPRESS	获取价格	1 of 2:4 Differential Clock/Data Fanout Buffer
CY2DP314OIT	CYPRESS	获取价格	1 of 2:4 Differential Clock/Data Fanout Buffer
CY2DP314OXI	CYPRESS	获取价格	1 of 2:4 Differential Clock/Data Fanout Buffer
CY2DP314OXIT	CYPRESS	获取价格	1 of 2:4 Differential Clock/Data Fanout Buffer
CY2DP814	CYPRESS	获取价格	1:4 Clock Fanout Buffer
CY2DP814_05	CYPRESS	获取价格	ComLink⑩ Series
CY2DP814_08	CYPRESS	获取价格	1:4 Clock Fanout Buffer
CY2DP814O	CYPRESS	获取价格	Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, SSOP-16
CY2DP814SC	CYPRESS	获取价格	1:4 Clock Fanout Buffer
CY2DP814SCT	CYPRESS	获取价格	1:4 Clock Fanout Buffer

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