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CY2DP814SC PDF预览

CY2DP814SC

更新时间: 2024-09-30 22:40:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 逻辑集成电路光电二极管驱动时钟
页数 文件大小 规格书
9页 122K
描述
1:4 Clock Fanout Buffer

CY2DP814SC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.150 INCH, SOIC-16
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.8输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:9.8933 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:16
实输出次数:4最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):240电源:3.3 V
Prop。Delay @ Nom-Sup:5 ns传播延迟(tpd):5 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.2 ns
座面最大高度:1.727 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm

CY2DP814SC 数据手册

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ComLink™ Series  
CY2DP814  
1:4 Clock Fanout Buffer  
Features  
Description  
Low voltage operation  
VDD = 3.3V  
1:4 fanout  
The Cypress CY2 series of network circuits are produced  
using advanced 0.35-micron CMOS technology, achieving the  
industrys fastest logic.  
The Cypress CY2DP814 fanout buffer features a single LVDS-  
or a single LVPECL-compatible input and four LVPECL output  
pairs.  
Single-input configurable for LVDS, LVPECL, or LVTTL  
Four differential pairs of LVPECL outputs  
Drives 50-ohm load  
Low input capacitance  
Low output skew  
Designed for data communications clock management appli-  
cations, the fanout from a single input reduces loading on the  
input clock.  
Low propagation delay  
The CY2DP814 is ideal for both level translations from  
single-ended to LVPECL and/or for the distribution of  
LVDS-based clock signals. The Cypress CY2DP814 has  
configurable input between logic families. The input can be  
selectable for an LVPECL/LVTTL or LVDS signal, while the  
output drivers support LVPECL capable of driving 50-ohm  
lines.  
Typical (tpd < 4 ns)  
Industrial versions available  
Available packages include TSSOP, SOIC  
Pin Configuration  
Block Diagram  
EN1 1  
EN2 8  
EN1  
CONFIG  
VDD  
Q1A  
Q1B  
16  
15  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
8
16 Q1A  
15 Q1B  
Q2A  
Q2B  
Q3A  
Q3B  
VDD  
14 Q2A  
13 Q2B  
IN+ 6  
GND  
IN+  
IN-  
7
IN-  
Q4A  
Q4B  
LVDS /  
12 Q3A  
11 Q3B  
LVPECL /  
LVTTL  
EN2  
CONFIG 2  
16 pin TSSOP / SOIC  
10 Q4A  
9 Q4B  
OUTPUT  
LVPECL  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-07060 Rev. *B  
Revised December 15, 2002  

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