CY2DP814SI

更新时间： 2024-09-30 22:40:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
9页	122K
描述
1:4 Clock Fanout Buffer

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CY2DP814SI 数据手册

ComLink™ Series

CY2DP814

1:4 Clock Fanout Buffer

Features

Description

• Low voltage operation

• V_DD= 3.3V

• 1:4 fanout

The Cypress CY2 series of network circuits are produced

using advanced 0.35-micron CMOS technology, achieving the

industry’s fastest logic.

The Cypress CY2DP814 fanout buffer features a single LVDS-

or a single LVPECL-compatible input and four LVPECL output

pairs.

• Single-input configurable for LVDS, LVPECL, or LVTTL

• Four differential pairs of LVPECL outputs

• Drives 50-ohm load

• Low input capacitance

• Low output skew

Designed for data communications clock management appli-

cations, the fanout from a single input reduces loading on the

input clock.

• Low propagation delay

The CY2DP814 is ideal for both level translations from

single-ended to LVPECL and/or for the distribution of

LVDS-based clock signals. The Cypress CY2DP814 has

configurable input between logic families. The input can be

selectable for an LVPECL/LVTTL or LVDS signal, while the

output drivers support LVPECL capable of driving 50-ohm

lines.

— Typical (tpd < 4 ns)

• Industrial versions available

• Available packages include TSSOP, SOIC

Pin Configuration

Block Diagram

EN1 1

EN2 8

EN1

CONFIG

VDD

Q1A

Q1B

16 Q1A

15 Q1B

Q2A

Q2B

Q3A

Q3B

VDD

14 Q2A

13 Q2B

IN+ 6

GND

IN+

IN-

Q4A

Q4B

LVDS /

12 Q3A

11 Q3B

LVPECL /

LVTTL

EN2

CONFIG 2

16 pin TSSOP / SOIC

10 Q4A

9 Q4B

OUTPUT

LVPECL

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07060 Rev. *B

Revised December 15, 2002

12 3 4 5 6 7...9

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CY2DP814SI 替代型号

型号	品牌	替代类型	描述	数据表
CY2DP814SC	CYPRESS	功能相似	1:4 Clock Fanout Buffer

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