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CY2DL1510AZC

更新时间: 2024-10-01 09:41:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
15页 366K
描述
1:10 Differential LVDS Fanout Buffer

CY2DL1510AZC 数据手册

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CY2DL1510  
1:10 Differential LVDS Fanout Buffer  
Features  
Functional Description  
Low-voltage differential signal (LVDS) input with on-chip 100-Ω  
The CY2DL1510 is an ultra-low noise, low-skew,  
low-propagation delay 1:10 differential LVDS fanout buffer  
targeted to meet the requirements of high-speed clock  
distribution applications. The on-chip 100-Ω input termination  
resistor reduces board component count, while the synchronous  
clock enable function ensures glitch-free output transitions  
during enable and disable periods. The device has a fully  
differential internal architecture that is optimized to achieve  
low-additive jitter and low-skew at operating frequencies of up to  
1.5 GHz.  
input termination resistor  
Ten differential LVDS outputs  
40-ps maximum output-to-output skew  
600-ps maximum propagation delay  
0.11-ps maximum additive RMS phase jitter at 156.25 MHz  
(12-kHz to 20-MHz offset)  
Up to 1.5-GHz operation  
Synchronous clock enable function  
32-pin thin quad flat pack (TQFP) package  
2.5-V or 3.3-V operating voltage[1]  
Commercial and industrial operating temperature range  
Logic Block Diagram  
Q0  
Q0#  
Q1  
Q1#  
VDD  
VSS  
Q2  
Q2#  
Q3  
Q3#  
Q4  
IN  
100  
Q4#  
IN#  
Q5  
Q5#  
VDD  
Q
100k  
D
Q6  
CLK_EN  
Q6#  
Q7  
Q7#  
VBB  
Q8  
Q8#  
Q9  
Q9#  
Note  
1. Input AC-coupling capacitors are required for voltage-translation applications.  
Cypress Semiconductor Corporation  
Document Number: 001-54863 Rev. *H  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised February 25, 2011  
[+] Feedback  

CY2DL1510AZC 替代型号

型号 品牌 替代类型 描述 数据表
CY2DL1510AZCT CYPRESS

完全替代

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