Datasheet > CY2DL814_05

CY2DL814_05

更新时间： 2024-10-01 04:13:19

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
8页	191K
描述
ComLink⑩ Series

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数据手册

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CY2DL814_05 数据手册

ComLink™ Series

CY2DL814

1:4 Clock Fanout Buffer

Features

Description

• Low-voltage operation

• V_DD= 3.3V

• 1:4 Fanout

• Single-input configurable for

— LVDS, LVPECL, or LVTTL

The Cypress CY2 series of network circuits is produced using

advanced 0.35-micron CMOS technology, achieving the

industry’s fastest logic.

The Cypress CY2DL814 fanout buffer features a single

LVDS-, LVPECL-, or LVTTL-compatible input and four LVDS

output pairs.

Designed for data-communication clock management applica-

tions, the fanout from a single input reduces loading on the

input clock.

The CY2DL814 is ideal for both level translations from single

ended to LVDS and/or for the distribution of LVDS-based clock

signals. The Cypress CY2DL814 has configurable input and

output functions. The input can be selectable for

LVPECL/LVTTL or LVDS signals while the output driver’s

support standard and high drive LVDS. Drive either a 50-ohm

or 100-ohm line with a single part number/device.

— Four differential pairs of LVDS outputs

• Drives 50- or 100-ohm load (selectable)

• Low input capacitance

• 85 ps typical output-to-output skew

• <4 ns typical propagation delay

• Does not exceed Bellcore 802.3 standards

• Operation at ⇒ 350 MHz – 700 Mbps

• Industrial versions available

• Packages available include TSSOP/SOIC

Block Diagram

Pin Configuration

EN1

EN2

EN1

Q1A

Q1B

CONFIG

CNTRL

VDD

Q1A

Q1B

Q2A

Q2B

Q3A

Q3B

Q4A

Q4B

GND

IN+

IN-

Q2A

Q2B

IN+

IN-

EN2

LVDS /

LVPECL /

LVTTL

Q3A

Q3B

16-pin TSSOP/SOIC

CONFIG

Q4A

Q4B

CNTRL

OUTPUT

LVDS

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07057 Rev. *B

Revised June 20, 2005

12 3 4 5 6 7 8

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