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CY2DL1504ZXCT PDF预览

CY2DL1504ZXCT

更新时间: 2024-11-25 09:41:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
14页 302K
描述
1:4 Differential LVDS Fanout Buffer with Selectable Clock Input

CY2DL1504ZXCT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP-20
针数:20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.31.00.01
Factory Lead Time:1 week风险等级:5.74
其他特性:ALSO OPERATES WITH 3.135V TO 3.465V SUPPLY系列:2DL
输入调节:DIFFERENTIAL MUXJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:6.5 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:20实输出次数:4
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:2.5/3.3 VProp。Delay @ Nom-Sup:0.48 ns
传播延迟(tpd):0.48 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.03 ns座面最大高度:1.1 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
最小 fmax:1500 MHzBase Number Matches:1

CY2DL1504ZXCT 数据手册

 浏览型号CY2DL1504ZXCT的Datasheet PDF文件第2页浏览型号CY2DL1504ZXCT的Datasheet PDF文件第3页浏览型号CY2DL1504ZXCT的Datasheet PDF文件第4页浏览型号CY2DL1504ZXCT的Datasheet PDF文件第5页浏览型号CY2DL1504ZXCT的Datasheet PDF文件第6页浏览型号CY2DL1504ZXCT的Datasheet PDF文件第7页 
CY2DL1504  
1:4 Differential LVDS Fanout Buffer  
with Selectable Clock Input  
Features  
Functional Description  
Select between low-voltage positive emitter-coupled logic  
(LVPECL) or low-voltage differential signal (LVDS) input pairs  
to distribute to four LVDS output pairs  
The CY2DL1504 is an ultra-low noise, low-skew,  
low-propagation delay 1:4 differential LVDS fanout buffer  
targeted to meet the requirements of high-speed clock  
distribution applications. The CY2DL1504 can select between  
LVPECL or LVDS input clock pairs using the IN_SEL pin. The  
synchronous clock enable function ensures glitch-free output  
transitions during enable and disable periods. The output enable  
function allows the outputs to be asynchronously driven to a  
high-impedance state. The device has a fully differential internal  
architecture that is optimized to achieve low-additive jitter and  
low-skew at operating frequencies of up to 1.5 GHz.  
30-ps maximum output-to-output skew  
480-ps maximum propagation delay  
0.11-ps maximum additive RMS phase jitter at 156.25 MHz  
(12-kHz to 20-MHz offset)  
Up to 1.5-GHz operation  
Output enable and synchronous clock enable functions  
20-pin thin shrunk small outline package (TSSOP)  
2.5-V or 3.3-V operating voltage[1]  
Commercial and industrial operating temperature range  
Logic Block Diagram  
VDD  
VSS  
Q0  
Q0#  
IN0  
IN0#  
Q1  
Q1#  
IN1  
IN1#  
Q2  
Q2#  
IN_SEL  
Q3  
Q3#  
RP  
VDD  
Q
RP  
D
CLK_EN  
VDD  
RP  
OE  
Note  
1. Input AC-coupling capacitors are required for voltage-translation applications.  
Cypress Semiconductor Corporation  
Document Number: 001-56312 Rev. *F  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 29, 2011  
[+] Feedback  

CY2DL1504ZXCT 替代型号

型号 品牌 替代类型 描述 数据表
CY2DL1504ZXIT CYPRESS

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