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CY2CP1504ZXI PDF预览

CY2CP1504ZXI

更新时间: 2024-10-01 09:41:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
13页 286K
描述
1:4 LVCMOS to LVPECL Fanout Buffer with Selectable Clock Input

CY2CP1504ZXI 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, SSOP20,.25
针数:20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.31.00.01
Factory Lead Time:1 week风险等级:8.55
Is Samacsys:N其他特性:ALSO OPERATES WITH 3.135V TO 3.465V SUPPLY
系列:2DL输入调节:MUX
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:6.5 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:4端子数量:20
实输出次数:4最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:SSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:2.5/3.3 V
Prop。Delay @ Nom-Sup:0.48 ns传播延迟(tpd):0.48 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.03 ns
座面最大高度:1.1 mm子类别:Clock Drivers
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mm最小 fmax:250 MHz
Base Number Matches:1

CY2CP1504ZXI 数据手册

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CY2CP1504  
1:4 LVCMOS to LVPECL Fanout Buffer  
with Selectable Clock Input  
Features  
Functional Description  
Select one of two low-voltage complementary metal oxide  
semiconductor (LVCMOS) inputs to distribute to four  
low-voltage positive emitter-coupled logic (LVPECL) output  
pairs  
The CY2CP1504 is an ultra-low noise, low-skew,  
low-propagation delay 1:4 LVCMOS to LVPECL fanout buffer  
targeted to meet the requirements of high-speed clock  
distribution applications. The CY2CP1504 can select between  
two separate LVCMOS input clocks using the IN_SEL pin. The  
synchronous clock enable function ensures glitch-free output  
transitions during enable and disable periods. The device has a  
fully differential internal architecture that is optimized to achieve  
low additive jitter and low skew at operating frequencies of up to  
250 MHz.  
30-ps maximum output-to-output skew  
480-ps maximum propagation delay  
0.15-ps maximum additive RMS phase jitter at 156.25 MHz  
(12-kHz to 20-MHz offset)  
Up to 250 MHz operation  
Synchronous clock enable function  
20-Pin thin shrunk small outline package (TSSOP) package  
2.5-V or 3.3-V operating voltage[1]  
Commercial and industrial operating temperature range  
Logic Block Diagram  
Q0  
Q0#  
VDD  
VSS  
Q1  
Q1#  
IN0  
IN1  
Q2  
Q2#  
Q3  
Q3#  
IN_SEL  
100k  
VDD  
100k  
Q
D
CLK_EN  
Note  
1. Input AC-coupling capacitors are required for voltage-translation applications.  
Cypress Semiconductor Corporation  
Document Number: 001-56313 Rev. *F  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised February 25, 2011  
[+] Feedback  

CY2CP1504ZXI 替代型号

型号 品牌 替代类型 描述 数据表
CY2CP1504ZXIT CYPRESS

完全替代

1:4 LVCMOS to LVPECL Fanout Buffer with Selectable Clock Input
CY2CP1504ZXCT CYPRESS

类似代替

1:4 LVCMOS to LVPECL Fanout Buffer with Selectable Clock Input
CY2CP1504ZXC CYPRESS

类似代替

1:4 LVCMOS to LVPECL Fanout Buffer with Selectable Clock Input

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