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CY2CC910OXIT

更新时间: 2024-10-01 03:24:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟
页数 文件大小 规格书
9页 218K
描述
1:10 Clock Fanout Buffer

CY2CC910OXIT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP, SSOP20,.3针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.79
其他特性:ALSO OPERATES WITH 2.5V AND 3.3V SUPPLY; CYPRS06929-1 REFFER THIS DATA SHEET FOR PACKAGE DIMENSIONS系列:2CC
输入调节:SCHMITT TRIGGERJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:7.2 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER最大I(ol):0.012 A
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:20
实输出次数:10最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP20,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:1.8/3.3 V
Prop。Delay @ Nom-Sup:3.5 ns传播延迟(tpd):3.5 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.2 ns
座面最大高度:2 mm子类别:Clock Drivers
最大供电电压 (Vsup):1.89 V最小供电电压 (Vsup):1.71 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:5.3 mm

CY2CC910OXIT 数据手册

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COMLINK™ SERIES  
CY2CC910  
1:10 Clock Fanout Buffer  
Features  
• Low-voltage operation  
Description  
The Cypress series of network circuits are produced using  
advanced 0.35 micron CMOS technology, achieving the indus-  
tries fastest logic and buffers.  
• Full-range support:  
— 3.3V  
The Cypress CY2CC910 fanout buffer features one input and  
ten outputs. Ideal for conversion from/to 3.3V/2.5V/1.8V  
— 2.5V  
— 1.8V  
Designed for Data Communications clock management appli-  
cations, the large fanout from a single input reduces loading  
on the input clock.  
• Over voltage tolerant input hot swappable  
• 1:10 fanout  
• Drives either a 50-Ohm or 75-Ohm load  
• Low-input capacitance  
• Low-output skew  
Cypress employs unique AVCMOS type outputs VOI™  
(Variable Output Impedance) that dynamically adjust for  
variable impedance matching and eliminate the need for  
series damping resistors and reduce noise overall.  
• Low-propagation delay  
• Typical (tpd < 4 ns)  
• High-speed operation:  
— 200 MHz@1.8V  
— 650 MHz@2.5V/3.3V  
• Industrial versions available  
• Available packages include: SOIC, SSOP  
Pin Configuration  
Block Diagram  
3
Q 1  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VDD  
IN  
1
2
3
4
5
6
7
8
5
7
Q10  
Q9  
Q 2  
Q 3  
Q 4  
Q 5  
Q 6  
Q 7  
Q 8  
Q 9  
Q 10  
GND  
Q1  
VDD  
Q2  
GND  
Q8  
VD D  
9
VDD  
Q7  
4,8  
15,20  
GND  
Q3  
11  
GND  
Q6  
VDD  
Q4  
IN  
1
9
10  
12  
14  
16  
18  
19  
Q5  
INPUT  
(AVCMOS)  
2,6,10  
GND  
20 pin SOIC/SSOP  
13,17  
G N D  
OUTPUT  
(AVCMOS)  
Cypress Semiconductor Corporation  
Document #: 38-07348 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised October 27, 2005  

CY2CC910OXIT 替代型号

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