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CY2CC910_08

更新时间: 2024-09-30 06:51:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟
页数 文件大小 规格书
11页 473K
描述
1:10 Clock Fanout Buffer

CY2CC910_08 数据手册

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CY2CC910  
1:10 Clock Fanout Buffer  
Features  
Description  
Low voltage operation  
The Cypress series of network circuits are produced using  
advanced 0.35 micron CMOS technology, achieving the  
industry’s fastest logic and buffers.  
Full range support:  
3.3V  
2.5V  
1.8V  
The Cypress CY2CC910 fanout buffer features one input and  
10 outputs. It is ideal for conversion from and to 3.3V, 2.5V,  
and 1.8V  
Over voltage tolerant input hot swappable  
Designed for Data Communications clock management appli-  
cations, the large fanout from a single input reduces loading  
on the input clock.  
1:10 Fanout  
Drives either a 50-Ohm or 75-Ohm load  
Cypress employs the unique AVCMOS type outputs VOI  
(Variable Output Impedance) that dynamically adjust for  
variable impedance matching, eliminate the need for series  
damping resistors, and reduce overall noise.  
Low input capacitance  
Low output skew  
Low propagation delay  
Typical (tpd less than 4 ns)  
High speed operation:  
200 MHz at1.8V  
650 MHz at 2.5V and 3.3V  
Industrial versions available  
Available packages include: SOIC, SSOP  
Logic Block Diagram  
3
Q 1  
5
Q 2  
7
Q 3  
VD D  
9
4,8  
15,20  
Q 4  
11  
Q 5  
IN  
1
12  
INPUT  
(AVCMOS)  
2,6,10  
13,17  
Q 6  
14  
Q 7  
16  
Q 8  
G N D  
18  
Q 9  
19  
Q 10  
OUTPUT  
(AVCMOS)  
Cypress Semiconductor Corporation  
Document #: 38-07348 Rev. *C  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised October 22, 2008  
[+] Feedback  

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