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CY2CC1910SCT PDF预览

CY2CC1910SCT

更新时间: 2024-11-24 22:10:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 131K
描述
1:10 Clock Fanout Buffer with Output Enable

CY2CC1910SCT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.300 INCH, SOIC-24
针数:24Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.92
Is Samacsys:N其他特性:ALSO OPERATES WITH 2.5V AND 3.3V SUPPLY
输入调节:SCHMITT TRIGGERJESD-30 代码:R-PDSO-G24
JESD-609代码:e0长度:15.3924 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER最大I(ol):0.002 A
功能数量:1反相输出次数:
端子数量:24实输出次数:10
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP24,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.8/3.3 VProp。Delay @ Nom-Sup:3.5 ns
传播延迟(tpd):3.5 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.2 ns座面最大高度:2.667 mm
子类别:Clock Drivers最大供电电压 (Vsup):1.89 V
最小供电电压 (Vsup):1.71 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

CY2CC1910SCT 数据手册

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COMLINK™ SERIES  
CY2CC1910  
1:10 Clock Fanout Buffer with Output Enable  
Features  
Description  
Low-voltage operation  
Full-range support:  
3.3V  
2.5V  
1.8V  
The Cypress series of network circuits are produced using  
advanced 0.35-micron CMOS technology, achieving the  
industries fastest logic and buffers.  
The Cypress CY2CC1910 fanout buffer features one input and  
ten outputs. Ideal for conversion from/to 3.3V/2.5V/1.8V.  
Designed for data communications clock management appli-  
cations, the large fanout from a single input reduces loading  
on the input clock.  
Cypress employs unique AVCMOS-type outputs VOI™  
(Variable Output Impedance) that dynamically adjust for  
variable impedance matching and eliminate the need for  
series damping resistors; they also reduce noise overall.  
1:10 fanout  
Drives either a 50-Ohm or 75-Ohm load  
Over voltage tolerant input hot swappable  
Low-input capacitance  
Low-output skew  
Low-propagation delay  
Typical (tpd < 4 ns)  
High-speed operation:  
100 MHz@1.8V  
200 MHz@2.5V/3.3V  
Industrial versions available  
Available packages include: SOIC, SSOP  
Block Diagram  
Pin Configuration  
23  
21  
5
Q1  
GND  
Q10  
VDD  
Q9  
GND  
Q1  
1
2
3
4
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
OE#  
AVCMOS  
VDD  
Q2  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
Q8  
Q9  
Q10  
19  
18  
OE#  
IN  
GND  
GND  
Q3  
Q4  
5
6
7
8
VDD  
GND  
Q8  
GND  
Q5  
VDD  
Q6  
3,10  
15,22  
9
16  
14  
11  
9
VDD  
Q7  
10  
11  
12  
6
GND  
GND  
1,12,13  
17,24  
IN  
AVCMOS  
24 pin SOIC/SSOP  
GND  
4
2
OUTPUT (AVCMOS)  
Pin Description  
Pin Number  
1, 7, 8, 12, 13, 17, 20, 24  
3,10,15,22  
Pin Name  
Pin Description  
Power  
GND  
VDD  
OE#  
IN  
Ground  
Power Supply  
Output Enable  
Input  
Power  
LVTTL/LVCMOS  
LVTTL/LVCMOS  
AVCMOS  
5
6
2, 4, 9, 11, 14, 16, 18, 19, 21, 23 Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1 Output  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-07347 Rev. *B  
Revised December 26, 2002  

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