CY23FS04ZC

更新时间： 2024-11-08 22:14:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
12页	217K
描述
Failsafe 2.5V/ 3.3V Zero Delay Buffer

阅读下载

中文翻译

获取价格

数据手册
替代型号

如果您发现信息不准确，欢迎纠错

CY23FS04ZC 数据手册

CY23FS04

Failsafe™ 2.5V/ 3.3V Zero Delay Buffer

Features

Functional Description

• Internal DCXO for continuous glitch-free operation

• Zero input-output propagation delay

• Low-jitter (< 35 ps RMS) outputs

• Low Output-to-Output skew (< 200 ps)

• 4.17 MHz–170 MHz reference input

• Supports industry standard input crystals

• 170 MHz outputs

The CY23FS04 is a FailSafe zero delay buffer with two

reference clock inputs and four phase-aligned outputs. The

device provides an optimum solution for applications where

continuous operation is required in the event of a primary clock

failure.

The continuous, glitch-free operation is achieved by using a

DCXO, which serves as a redundant clock source in the event

of a reference clock failure by maintaining the last frequency

and phase information of the reference clock.

• 5V-tolerant inputs

• Phase-locked loop (PLL) Bypass Mode

• Dual Reference Inputs

The unique feature of the CY23FS04 is that the DCXO is in

fact the primary clocking source, which is synchronized

(phase-aligned) to the external reference clock. When this

external clock is restored, the DCXO automatically resynchro-

nizes to the external clock.

• 16-pin TSSOP

The frequency of the crystal, which will be connected to the

DCXO must be chosen to be an integer factor of the frequency

of the reference clock. This factor is set by two select lines:

S[2:1], please see Table 1. Output power supply, VDD can be

connected to either 2.5V or 3.3V. VDDC is the power supply

pin for internal circuits and must be connected to 3.3V.

• 2.5V or 3.3V output power supplies

• 3.3V core power supply

• Industrial temperature available

Block Diagram

Pin Configuration

XIN XOUT

REF1

REF2

CLKB1

CLKB2

VSS

VDDC

XIN

REFSEL

FBK

CLKA1

CLKA2

VDD

FAIL#/SAFE

XOUT

REFSEL

DCXO

REF1

CLKA[1:2]

CLKB[1:2]

Failsafe^TM

REF2

FBK

PLL

Block

16 pin TSSOP

Decoder

FAIL# /SAFE

S[2:1]

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07304 Rev. *B

Revised October 12, 2004

12 3 4 5 6 7...12

中文翻译

下载PDF

CY23FS04ZC 替代型号

型号	品牌	替代类型	描述	数据表
CY23FS04ZI	CYPRESS	完全替代	Failsafe 2.5V/ 3.3V Zero Delay Buffer
CY23FS04ZXI	CYPRESS	功能相似	Failsafe⑩ 2.5V/ 3.3V Zero Delay Buffer
CY23FS04ZXC	CYPRESS	功能相似	Failsafe⑩ 2.5V/ 3.3V Zero Delay Buffer

与CY23FS04ZC相关器件

型号	品牌	获取价格	描述	数据表
CY23FS04ZCT	CYPRESS	获取价格	Failsafe 2.5V/ 3.3V Zero Delay Buffer
CY23FS04ZI	CYPRESS	获取价格	Failsafe 2.5V/ 3.3V Zero Delay Buffer
CY23FS04ZIT	CYPRESS	获取价格	Failsafe 2.5V/ 3.3V Zero Delay Buffer
CY23FS04ZXC	CYPRESS	获取价格	Failsafe⑩ 2.5V/ 3.3V Zero Delay Buffer
CY23FS04ZXC-2	CYPRESS	获取价格	Failsafeâ¢ 2.5V/3.3V Zero Delay Buffer
CY23FS04ZXC-2T	CYPRESS	获取价格	Failsafeâ¢ 2.5V/3.3V Zero Delay Buffer
CY23FS04ZXCT	CYPRESS	获取价格	Failsafe⑩ 2.5V/ 3.3V Zero Delay Buffer
CY23FS04ZXI	CYPRESS	获取价格	Failsafe⑩ 2.5V/ 3.3V Zero Delay Buffer
CY23FS04ZXI-3	CYPRESS	获取价格	Failsafeâ¢ 2.5 V/3.3 V Zero Delay Buffer
CY23FS04ZXI-3T	CYPRESS	获取价格	Clock Driver, ECL Series, 2 True Output(s), 0 Inverted Output(s), PDSO16, 4.40 MM, LEAD FR

与CY23FS04ZC相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

22
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

21
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

47
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

39

产品中心

服务支持

精选活动

关于我们

帮助中心

CY23FS04ZC

CY23FS04ZC 数据手册

CY23FS04ZC 替代型号

与CY23FS04ZC相关器件

与CY23FS04ZC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY23FS04ZC

CY23FS04ZC 数据手册

CY23FS04ZC 替代型号

与CY23FS04ZC相关器件

与CY23FS04ZC相关文章

您还可以找

您在本页遇到什么问题？